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LCMXO2-2000HC-4TG144I - Lattice Semiconductor

Description: Lattice Semiconductor LCMXO2-2000HC-4TG144I, CPLD MachXO2 Flash 111 I/O, 2112 Labs, 7.24ns, ISP, 144-Pin TQFP

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LCMXO2-2000HC-4TG144I Details

  • Manufacturer Part Number:

    LCMXO2-2000HC-4TG144I

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    QFP

  • Pin Count:

    144

  • Country Of Origin:

    Malaysia, Philippines, Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    19

  • Additional Feature:

    ALSO OPERATES AT 3.3 V NOMINAL SUPPLY

  • Clock Frequency-Max:

    130.5 MHz

  • JESD-30 Code:

    S-PQFP-G144

  • JESD-609 Code:

    e3

  • Length:

    20 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    264

  • Number of Inputs:

    111

  • Number of Logic Cells:

    2112

  • Number of Outputs:

    111

  • Number of Terminals:

    144

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    264 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    QFP

  • Package Equivalence Code:

    QFP144,.87SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK

  • Packing Method:

    TRAY

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max:

    3.465 V

  • Supply Voltage-Min:

    2.375 V

  • Supply Voltage-Nom:

    2.5 V

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    20 mm

LCMXO2-2000HC-4TG144I Frequently Asked Questions (FAQs)

  • The LCMXO2-2000HC-4TG144I has an operating temperature range of -40°C to 100°C.
  • You can implement a clock tree using the FPGA's built-in clock management resources, such as the Phase-Locked Loop (PLL) and the Clock Management Unit (CMU). The Lattice Diamond software provides tools to help you design and implement a clock tree.
  • The maximum frequency of the FPGA's I/Os is 480 Mbps, but this can vary depending on the specific I/O standard and the system design.
  • You can configure the FPGA's power management using the Lattice Diamond software, which provides tools to help you optimize power consumption and reduce power noise. You can also use the FPGA's built-in power management features, such as the Power Management Unit (PMU).
  • The LCMXO2-2000HC-4TG144I has 2000 LUTs (Look-Up Tables) and 144 Kbits of EBR (Embedded Block RAM).

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LCMXO2-2000HC-4TG144I Overview

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