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LFE2M100E-5FN900I - Lattice Semiconductor

Description: FPGA - Field Programmable Gate Array 95K LUTs 416 I/O Memory DSP 1.2V 5SPD

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LFE2M100E-5FN900I Details

  • Manufacturer Part Number:

    LFE2M100E-5FN900I

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    BGA

  • Package Description:

    FPBGA-900

  • Pin Count:

    900

  • Country Of Origin:

    Malaysia, Philippines, Taiwan

  • ECCN Code:

    3A991.D

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    9

  • Clock Frequency-Max:

    311 MHz

  • Combinatorial Delay of a CLB-Max:

    0.358 ns

  • JESD-30 Code:

    S-PBGA-B900

  • JESD-609 Code:

    e1

  • Length:

    31 mm

  • Moisture Sensitivity Level:

    3

  • Number of Inputs:

    416

  • Number of Logic Cells:

    100000

  • Number of Outputs:

    416

  • Number of Terminals:

    900

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    11875 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA900,30X30,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Width:

    31 mm

LFE2M100E-5FN900I Frequently Asked Questions (FAQs)

  • The LFE2M100E-5FN900I has an industrial temperature range of -40°C to 100°C, making it suitable for use in a wide range of applications.
  • The LFE2M100E-5FN900I has a dedicated clock management system that allows for the creation of a clock tree using the ispLEVER or Lattice Diamond design software. The FPGA also has a number of clocking resources, including phase-locked loops (PLLs) and clock buffers, to help implement a robust clock tree.
  • The power consumption of the LFE2M100E-5FN900I depends on the specific application and usage. However, according to the datasheet, the typical static power consumption is around 100-150 mW, and the dynamic power consumption can range from 100-500 mW depending on the clock frequency and toggle rate.
  • Yes, the LFE2M100E-5FN900I has high-speed I/O capabilities, including support for PCIe Gen1 and SATA II interfaces. The FPGA also has a number of high-speed transceivers that can be used to implement these interfaces.
  • The LFE2M100E-5FN900I can be programmed and configured using the Lattice Diamond or ispLEVER design software. The FPGA can be configured using a variety of methods, including JTAG, SPI, and I2C. The device can also be reconfigured in the field using partial reconfiguration.

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LFE2M100E-5FN900I Overview

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Part Image LFE2M100E-5F900I Lattice Semiconductor Corporation

Field Programmable Gate Array, 11875 CLBS, 311MHz, 100000-Cell, PBGA900