Part Image

LFE3-35EA-7FN484C - Lattice Semiconductor

Description: FPGA LatticeECP3 Family 33000 Cells 65nm Technology 1.2V 484-Pin FBGA

Download LFE3-35EA-7FN484C Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
PCB Footprints
LFE3-35EA-7FN484C - Lattice Semiconductor PCB footprint - BGA - BGA - 484-Ball fpBGA
click to zoom
3D Models
LFE3-35EA-7FN484C - Lattice Semiconductor  - 3D model - BGA - 484-Ball fpBGA
click to zoom

LFE3-35EA-7FN484C Details

  • Manufacturer Part Number:

    LFE3-35EA-7FN484C

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    BGA

  • Pin Count:

    484

  • Country Of Origin:

    Malaysia, Philippines, Taiwan

  • ECCN Code:

    3A991.D

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    9

  • Clock Frequency-Max:

    2932 MHz

  • Combinatorial Delay of a CLB-Max:

    0.335 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    4125

  • Number of Inputs:

    295

  • Number of Logic Cells:

    33000

  • Number of Outputs:

    295

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    85 °C

  • Organization:

    4125 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    23 mm

LFE3-35EA-7FN484C Frequently Asked Questions (FAQs)

  • The LFE3-35EA-7FN484C FPGA has an operating temperature range of -40°C to 100°C.
  • You can implement a clock tree using the FPGA's dedicated clock resources, including the Clock Management Unit (CMU) and the Phase-Locked Loop (PLL) blocks. The Lattice Diamond design software provides tools and IP cores to help you design and implement a clock tree.
  • The maximum frequency achievable with the LFE3-35EA-7FN484C FPGA depends on the specific design and implementation. However, the FPGA has a maximum clock frequency of 500 MHz for the fabric clock and 1 GHz for the PLL output.
  • You can configure the FPGA's I/O banks using the Lattice Diamond design software. The software provides a graphical interface to configure the I/O banks, including setting the voltage levels, termination, and slew rates.
  • The power consumption of the LFE3-35EA-7FN484C FPGA depends on the specific design and implementation. However, the FPGA has a typical static power consumption of 100 mW and a dynamic power consumption of 100 mW/MHz.

Trust Checks

This model has been provided by community users.
Community Provided
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored

LFE3-35EA-7FN484C Overview

Use the download button to access the LFE3-35EA-7FN484C schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like LFE3-, or try a keyword search, such as Field Programmable Gate Arrays

Parts related to LFE3-35EA-7FN484C

Showing 0 results

LFE3-35EA-7FN484C Alternates

Showing results

Image Part Number Model
Part Image LFE3-35EA-7FN484I Lattice Semiconductor Corporation

Field Programmable Gate Array