Part Image

LTC2140IUP-12#PBF - Analog Devices

Description: 12-Bit, 25Msps Low Power Dual ADCs

Download LTC2140IUP-12#PBF Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
PCB Footprints
LTC2140IUP-12#PBF - Analog Devices PCB footprint - Quad Flat No-Lead - Quad Flat No-Lead - UP Package 64-Lead Plastic QFN (9mm × 9mm)
click to zoom
3D Models
LTC2140IUP-12#PBF - Analog Devices  - 3D model - Quad Flat No-Lead - UP Package 64-Lead Plastic QFN (9mm × 9mm)
click to zoom

LTC2140IUP-12#PBF Details

  • Manufacturer Part Number:

    LTC2140IUP-12#PBF

  • Brand Name:

    Analog Devices Inc

  • Pbfree Code:

    No

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64

  • Pin Count:

    64

  • Manufacturer Package Code:

    05-08-1705

  • Country Of Origin:

    Thailand

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Analog Devices Inc

  • YTEOL:

    10

  • Analog Input Voltage-Max:

    1.25 V

  • Analog Input Voltage-Min:

    0.7 V

  • Converter Type:

    ADC, PROPRIETARY METHOD

  • JESD-30 Code:

    S-PQCC-N64

  • JESD-609 Code:

    e3

  • Length:

    9 mm

  • Linearity Error-Max (EL):

    0.022%

  • Moisture Sensitivity Level:

    1

  • Number of Analog In Channels:

    2

  • Number of Bits:

    12

  • Number of Functions:

    1

  • Number of Terminals:

    64

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Bit Code:

    OFFSET BINARY, 2S COMPLEMENT BINARY

  • Output Format:

    PARALLEL, WORD

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    HVQCCN

  • Package Equivalence Code:

    LCC64,.35SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Sample Rate:

    25 MHz

  • Sample and Hold / Track and Hold:

    SAMPLE

  • Seated Height-Max:

    0.8 mm

  • Supply Current-Max:

    32 mA

  • Supply Voltage-Nom:

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    NO LEAD

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    9 mm

LTC2140IUP-12#PBF Frequently Asked Questions (FAQs)

  • A good PCB layout for the LTC2140IUP-12 involves keeping the analog and digital grounds separate, using a solid ground plane, and minimizing the length of the input traces to reduce noise and parasitic inductance. A 4-layer PCB with a dedicated analog ground layer is recommended.
  • The LTC2140IUP-12 requires a clean and stable power supply. Use a low-ESR capacitor (e.g., 0.1uF ceramic) between the VCC and GND pins, and a 10uF capacitor between the VCC and AVCC pins. Additionally, use a separate analog power supply or a well-regulated switching power supply to minimize noise and ripple.
  • The maximum clock frequency for the LTC2140IUP-12 is 100MHz. However, the actual clock frequency may be limited by the specific application and the quality of the clock signal. It's recommended to use a high-quality clock source and to follow the clock signal integrity guidelines in the datasheet.
  • To optimize the performance of the LTC2140IUP-12 in a high-temperature environment, ensure good thermal management by providing adequate heat sinking and airflow. Use a thermally conductive material (e.g., thermal tape or thermal grease) to improve heat transfer between the device and the heat sink. Additionally, consider using a temperature-compensated voltage reference and ensuring that the device is operated within its specified temperature range.
  • The clock input of the LTC2140IUP-12 should be driven with a low-skew, low-jitter clock signal. A differential clock signal is recommended, with a peak-to-peak amplitude of 1.4V to 2.4V. The clock signal should be terminated with a 50Ω resistor to match the impedance of the clock input.

Trust Checks

This model has been built in collaboration with the manufacturer.
Manufacturer Collaborated
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored

LTC2140IUP-12#PBF Overview

Use the download button to access the LTC2140IUP-12#PBF schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like LTC21, or try a keyword search, such as Analog to Digital Converters

About Analog Devices

Analog Devices Inc. is a global leader in the design and manufacturing of analog, mixed-signal, and digital signal processing integrated circuits and software solutions for the industrial, automotive, healthcare, communications industries. Analog Devices serves a diverse range of markets including industrial, automotive, healthcare, energy, aerospace, defense, and consumer electronics industries. Analog Devices’ product portfolio includes a wide range of ICs, modules, and subsystems.

Parts related to LTC2140IUP-12#PBF

Showing 0 results

LTC2140IUP-12#PBF Alternates

Showing results

Image Part Number Model
Part Image LTC2140IUP-12#PBF Linear Technology

ADC, Proprietary Method, 12-Bit, 1 Func, 2 Channel, Parallel, Word Access, CMOS, PQCC64