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M2GL005-VFG256 - Microsemi Corporation

Description: FPGA IGLOO®2 Family 6060 Cells 1.2V 256-Pin VFBGA Tray

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M2GL005-VFG256 - Microsemi Corporation PCB footprint - BGA - BGA - VF256
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M2GL005-VFG256 - Microsemi Corporation  - 3D model - BGA - VF256
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M2GL005-VFG256 Details

  • Manufacturer Part Number:

    M2GL005-VFG256

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    14 X 14 MM, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-256

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Microsemi Corporation (now Microchip)

  • JESD-30 Code:

    S-PBGA-B256

  • Length:

    14 mm

  • Moisture Sensitivity Level:

    3

  • Number of Terminals:

    256

  • Operating Temperature-Max:

    85 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFBGA

  • Package Equivalence Code:

    BGA256,16X16,32

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1.56 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    14 mm

M2GL005-VFG256 Frequently Asked Questions (FAQs)

  • Microsemi recommends a 4-6 layer PCB stackup with a solid ground plane, and to follow the PCB layout guidelines provided in the M2GL005-VFG256 PCB Design Guide.
  • Use a multi-layer PCB with a solid power plane, and follow the PDN design guidelines in the M2GL005-VFG256 Power Distribution Network Application Note.
  • The FPGA has a maximum junction temperature of 100°C. Ensure good airflow, use a heat sink if necessary, and follow the thermal management guidelines in the M2GL005-VFG256 Thermal Management Application Note.
  • Use the Clocking Architecture Guide for M2GL005-VFG256, and follow the recommended clocking schemes and PLL settings for optimal performance and low jitter.
  • Refer to the M2GL005-VFG256 I/O Bank and Voltage Regulator Settings Application Note for recommended settings and configuration guidelines.

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M2GL005-VFG256 Overview

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