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M2S090TS-1FCS325I - Microsemi Corporation

Description: FPGA SmartFusion2 Family 86184 Cells 65nm Technology 1.2V 325-Pin FCBGA Tray

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M2S090TS-1FCS325I - Microsemi Corporation PCB footprint - BGA - BGA - 325 FCS 11x14
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3D Models
M2S090TS-1FCS325I - Microsemi Corporation  - 3D model - BGA - 325 FCS 11x14
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M2S090TS-1FCS325I Details

  • Manufacturer Part Number:

    M2S090TS-1FCS325I

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    FBGA-325

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Microsemi Corporation (now Microchip)

  • Additional Feature:

    LG-MIN, WD-MIN

  • JESD-30 Code:

    R-PBGA-B325

  • JESD-609 Code:

    e0

  • Length:

    13.5 mm

  • Number of Inputs:

    180

  • Number of Logic Cells:

    86316

  • Number of Outputs:

    180

  • Number of Terminals:

    325

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TFBGA

  • Package Equivalence Code:

    BGA325,21X21,20

  • Package Shape:

    RECTANGULAR

  • Package Style:

    GRID ARRAY, THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    240

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.16 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Tin/Lead (Sn/Pb)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    11 mm

M2S090TS-1FCS325I Frequently Asked Questions (FAQs)

  • The M2S090TS-1FCS325I FPGA has an operating temperature range of -40°C to 100°C.
  • To implement a CDC in the M2S090TS-1FCS325I, use the built-in clock domain crossing circuits or implement a synchronous FIFO to transfer data between clock domains.
  • The internal oscillator of the M2S090TS-1FCS325I FPGA has a maximum frequency of 100 MHz.
  • Yes, the M2S090TS-1FCS325I FPGA's PLL can generate multiple clock frequencies, allowing for flexible clock management.
  • To configure the I/O banks for 1.8V or 2.5V operation, use the FPGA's configuration software to set the I/O bank voltage and select the appropriate I/O standard.

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M2S090TS-1FCS325I Overview

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