MPC9658AC - Renesas Electronics
Description: The MPC9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and
