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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	MPC9608AC Renesas Electronics	1	The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs.	Quad Flat Packages	MPC9608AC	3D model available Symbol and footprint available 3	1 Download Model
	MPC961PAC Renesas Electronics	1	The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.	Quad Flat Packages	MPC961PAC	3D model available Symbol and footprint available 3	1 Download Model
	MPC9658AC Renesas Electronics	1	The MPC9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and	Quad Flat Packages	MPC9658AC	3D model available Symbol and footprint available 3	1 Download Model
	MPC962305EF-1HR2 Renesas Electronics	1	The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0	Small Outline Packages	MPC962305EF-1HR2	3D model available Symbol and footprint available 3	1 Download Model

	MPC962305EF-1H Renesas Electronics	1	The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0	Small Outline Packages	MPC962305EF-1H	3D model available Symbol and footprint available 3	1 Download Model
	MPC9600AE Renesas Electronics	1	The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock driver. The MPC9600 has the capability to generate clock signals of 50 to 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN.	Quad Flat Packages	MPC9600AE	3D model available Symbol and footprint available 3	1 Download Model
	MPC962309DT-1H Renesas Electronics	1	Renesas Electronics	Small Outline Packages	MPC962309DT-1H	3D model available Symbol and footprint available 3	1 Download Model
	MPC962309DT-1HR2 Renesas Electronics	1	Renesas Electronics	Small Outline Packages	MPC962309DT-1HR2	3D model available Symbol and footprint available 3	1 Download Model
	MPC961PACR2 Renesas Electronics	1	The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.	Quad Flat Packages	MPC961PACR2	3D model available Symbol and footprint available 3	1 Download Model
	MPC9600FA Renesas Electronics	1	Renesas Electronics	Quad Flat Packages	MPC9600FA	3D model available Symbol and footprint available 3	1 Download Model
	MPC9608ACR2 Renesas Electronics	1	Clock Buffer 10 LVCMOS OUT BUFFER	Quad Flat Packages	MPC9608ACR2	3D model available Symbol and footprint available 3	1 Download Model
	MPC9600AER2 Renesas Electronics	1	The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock driver. The MPC9600 has the capability to generate clock signals of 50 to 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN.	Quad Flat Packages	MPC9600AER2	3D model available Symbol and footprint available 3	1 Download Model
	MPC9658FA Renesas Electronics Corporation	1	PLL Based Clock Driver, MPC9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32		MPC9658FA	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC9653AFA Renesas Electronics Corporation	1	PLL Based Clock Driver, MPC9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32		MPC9653AFA	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC9608FA Renesas Electronics Corporation	1	PLL Based Clock Driver, MPC9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32		MPC9608FA	3D model not available Symbol and footprint not available 0	0 Build or Request

	MPC9653AAC Renesas Electronics Corporation	1	PLL Based Clock Driver, MPC9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32		MPC9653AAC	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC962308D-2 Freescale Semiconductor	1	PLL Based Clock Driver, 962308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16		MPC962308D-2	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC961CFAR2 Freescale Semiconductor	1	PLL Based Clock Driver, 961 Series, 17 True Output(s), 0 Inverted Output(s), BICMOS, PQFP32		MPC961CFAR2	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC962308EF-1HR2 Freescale Semiconductor	1	PLL Based Clock Driver, 962308 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16		MPC962308EF-1HR2	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC962308D-3R2 Motorola Semiconductor Products	1	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16		MPC962308D-3R2	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC962309D-1R2 Integrated Device Technology Inc	1	PLL Based Clock Driver, 962309 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16		MPC962309D-1R2	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC962305EJ-1HR2 Integrated Device Technology Inc	1	PLL Based Clock Driver, 962305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8		MPC962305EJ-1HR2	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC962308D-3 Motorola Semiconductor Products	1	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16		MPC962308D-3	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC9608FA Motorola Semiconductor Products	1	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32		MPC9608FA	3D model not available Symbol and footprint not available 0	0 Build or Request
	MPC9653FAR2 Freescale Semiconductor	1	PLL Based Clock Driver, 9653 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32		MPC9653FAR2	3D model not available Symbol and footprint not available 0	0 Build or Request
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