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NGTG30N60FWG - onsemi

Description: Obsolete - IGBT, 650V 35A FS2 Solar/UPS

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PCB Footprints
NGTG30N60FWG - onsemi PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - TO-247 CASE 340L-02
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3D Models
NGTG30N60FWG - onsemi  - 3D model - Transistor Outline, Vertical - TO-247 CASE 340L-02
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NGTG30N60FWG Details

  • Manufacturer Part Number:

    NGTG30N60FWG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TO-247

  • Pin Count:

    3

  • Manufacturer Package Code:

    340L-02

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    4 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    0

  • Collector Current-Max (IC):

    60 A

  • Collector-Emitter Voltage-Max:

    600 V

  • Gate-Emitter Thr Voltage-Max:

    6.5 V

  • Gate-Emitter Voltage-Max:

    20 V

  • JESD-609 Code:

    e3

  • Operating Temperature-Max:

    150 °C

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    167 W

  • Surface Mount:

    NO

  • Terminal Finish:

    Tin (Sn)

NGTG30N60FWG Frequently Asked Questions (FAQs)

  • The maximum junction temperature (Tj) for the NGTG30N60FWG is 175°C, as specified in the datasheet. However, it's recommended to keep the junction temperature below 150°C for reliable operation and to prevent thermal runaway.
  • To ensure proper cooling, a heat sink with a thermal resistance of less than 1°C/W is recommended. The heat sink should be attached to the device using a thermal interface material (TIM) with a thermal conductivity of at least 1 W/m-K. Additionally, ensure good airflow around the heat sink to dissipate heat efficiently.
  • The recommended gate drive voltage for the NGTG30N60FWG is between 10V and 15V. A higher gate drive voltage can improve switching performance, but may also increase power consumption and EMI emissions.
  • To protect the NGTG30N60FWG from overvoltage and overcurrent, use a voltage clamp or a transient voltage suppressor (TVS) to limit the voltage across the device. Additionally, use a current sense resistor and a fuse or a current limiter to prevent overcurrent conditions.
  • To minimize parasitic inductance and capacitance, use a compact PCB layout with short, wide traces for the power connections. Keep the gate drive circuitry close to the device and use a ground plane to reduce noise and EMI emissions.

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NGTG30N60FWG Overview

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