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SGW15N120 - Infineon

Description: IGBT NPT 1200 V 30 A 198 W Through Hole PG-TO247-3-1

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PCB Footprints
SGW15N120 - Infineon PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - PG-TO- 247-3
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3D Models
SGW15N120 - Infineon  - 3D model - Transistor Outline, Vertical - PG-TO- 247-3
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SGW15N120 Details

  • Manufacturer Part Number:

    SGW15N120

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TO-247AC

  • Pin Count:

    3

  • ECCN Code:

    EAR99

  • Manufacturer:

    Infineon Technologies AG

  • YTEOL:

    0

  • Case Connection:

    COLLECTOR

  • Collector Current-Max (IC):

    30 A

  • Collector-Emitter Voltage-Max:

    1200 V

  • Configuration:

    SINGLE

  • Fall Time-Max (tf):

    26 ns

  • Gate-Emitter Thr Voltage-Max:

    5 V

  • Gate-Emitter Voltage-Max:

    20 V

  • JEDEC-95 Code:

    TO-247AC

  • JESD-30 Code:

    R-PSFM-T3

  • Number of Elements:

    1

  • Number of Terminals:

    3

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLANGE MOUNT

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    198 W

  • Qualification Status:

    Not Qualified

  • Rise Time-Max (tr):

    24 ns

  • Surface Mount:

    NO

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    SINGLE

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Transistor Application:

    POWER CONTROL

  • Transistor Element Material:

    SILICON

  • Turn-off Time-Nom (toff):

    683 ns

  • Turn-on Time-Nom (ton):

    68 ns

SGW15N120 Frequently Asked Questions (FAQs)

  • The maximum allowed voltage imbalance between the DC links is ±10% of the nominal DC voltage. Exceeding this limit may lead to uneven current sharing and reduced module reliability.
  • Proper thermal management involves ensuring good heat sink contact, using a suitable thermal interface material, and maintaining a maximum junction temperature of 150°C. A heat sink with a thermal resistance of ≤0.5 K/W is recommended.
  • The recommended gate resistor value is between 10 Ω and 20 Ω. A higher value may lead to slower switching, while a lower value may cause oscillations.
  • Yes, the SGW15N120 can be used in a parallel configuration, but it's essential to ensure that the modules are matched in terms of electrical characteristics and thermal performance to avoid uneven current sharing.
  • The maximum allowed dv/dt for the SGW15N120 is 10 kV/μs. Exceeding this limit may lead to faulty operation or even damage to the module.

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SGW15N120 Overview

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