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SSM6L39TU,LF - Toshiba

Description: X34 PB-F UF6 S-MOS (LF) TRANSI

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SSM6L39TU,LF - Toshiba - PCB symbol
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PCB Footprints
SSM6L39TU,LF - Toshiba PCB footprint - SO Transistor Flat Lead - SO Transistor Flat Lead - SSM6L39TU
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3D Models
SSM6L39TU,LF - Toshiba - 3D model - SO Transistor Flat Lead - SSM6L39TU
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SSM6L39TU,LF Details

  • Manufacturer Part Number:

    SSM6L39TU,LF

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Not Recommended

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    16 Weeks

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    3

  • Configuration:

    SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    20 V

  • Drain Current-Max (ID):

    1.6 A

  • Drain-source On Resistance-Max:

    0.139 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    37 pF

  • JESD-30 Code:

    R-PDSO-F6

  • Number of Elements:

    2

  • Number of Terminals:

    6

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Polarity/Channel Type:

    N-CHANNEL AND P-CHANNEL

  • Power Dissipation-Max (Abs):

    0.5 W

  • Surface Mount:

    YES

  • Terminal Form:

    FLAT

  • Terminal Position:

    DUAL

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

SSM6L39TU,LF Frequently Asked Questions (FAQs)

  • A thermal pad is recommended under the package to improve heat dissipation. A minimum of 2oz copper thickness and a thermal relief pattern are recommended for optimal thermal performance.
  • Ensure that the device is operated within the recommended temperature range (−40°C to 150°C). Use a heat sink or thermal interface material to reduce thermal resistance. Avoid exceeding the maximum junction temperature (Tj) of 150°C.
  • A 10uF to 22uF X5R or X7R ceramic capacitor is recommended for input decoupling. The capacitor should be placed as close to the device as possible to minimize parasitic inductance.
  • Use a shielded enclosure, keep the device away from noise sources, and use a common-mode choke or ferrite bead to filter the input. Ensure that the PCB layout is optimized for minimal radiation and susceptibility.
  • A 10uF to 22uF X5R or X7R ceramic capacitor is recommended for output filtering. The capacitor should be placed as close to the device as possible to minimize parasitic inductance.

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SSM6L39TU,LF Overview

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