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TK60S06K3L - Toshiba

Description: N-ch MOSFET, 60 V, 60 A, 0.008 Ω@10V, DPAK+

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TK60S06K3L - Toshiba PCB footprint - Other - Other - 2-7M1A
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TK60S06K3L - Toshiba  - 3D model - Other - 2-7M1A
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TK60S06K3L Details

  • Manufacturer Part Number:

    TK60S06K3L

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Not Recommended

  • ECCN Code:

    EAR99

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    3

  • Avalanche Energy Rating (Eas):

    89 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    60 V

  • Drain Current-Max (ID):

    60 A

  • Drain-source On Resistance-Max:

    0.0123 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JESD-30 Code:

    R-PSSO-G2

  • Number of Elements:

    1

  • Number of Terminals:

    2

  • Operating Mode:

    ENHANCEMENT MODE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Polarity/Channel Type:

    N-CHANNEL

  • Pulsed Drain Current-Max (IDM):

    120 A

  • Reference Standard:

    AEC-Q101

  • Surface Mount:

    YES

  • Terminal Form:

    GULL WING

  • Terminal Position:

    SINGLE

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

TK60S06K3L Frequently Asked Questions (FAQs)

  • Toshiba recommends a PCB layout with a thermal pad connected to a large copper area on the bottom layer, and multiple vias to dissipate heat. A minimum of 2oz copper thickness is recommended.
  • Ensure proper heat sinking, use a thermal interface material, and follow the recommended PCB layout. Also, derate the device's power dissipation according to the temperature derating curve in the datasheet.
  • The maximum allowed voltage on the gate pin is ±20V, but it's recommended to keep it within ±15V to ensure reliable operation and prevent damage.
  • Yes, the TK60S06K3L is suitable for high-frequency switching applications up to 100kHz. However, ensure proper layout and decoupling to minimize parasitic inductance and capacitance.
  • Use a TVS diode or a zener diode in parallel with the MOSFET to clamp voltage spikes and transients. Also, consider adding a snubber circuit to reduce voltage ringing.

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TK60S06K3L Overview

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