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XC6SLX25-2FGG484I - AMD

Description: FPGA - Field Programmable Gate Array

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XC6SLX25-2FGG484I - AMD PCB footprint - BGA - BGA - FGG484-1
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XC6SLX25-2FGG484I - AMD  - 3D model - BGA - FGG484-1
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XC6SLX25-2FGG484I Details

  • Manufacturer Part Number:

    XC6SLX25-2FGG484I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    FPBGA-484

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    12 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    4

  • Clock Frequency-Max:

    667 MHz

  • Combinatorial Delay of a CLB-Max:

    0.26 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    1879

  • Number of Inputs:

    266

  • Number of Logic Cells:

    24051

  • Number of Outputs:

    266

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    1879 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 40 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    23 mm

XC6SLX25-2FGG484I Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the XC6SLX25 is 350 MHz.
  • You can implement a DDR3 memory interface on the XC6SLX25 using the MIG (Memory Interface Generator) tool provided by Xilinx. The tool generates a customized DDR3 controller IP core that can be integrated into your design.
  • The power consumption of the XC6SLX25 depends on the specific application and operating conditions. However, according to the datasheet, the typical power consumption is around 1.2W for a typical design.
  • Yes, the XC6SLX25 is suitable for high-reliability applications. It has a number of features that make it suitable for such applications, including built-in error correction, redundant logic, and a high level of fault tolerance.
  • You can debug your design on the XC6SLX25 using the Xilinx ChipScope Pro tool. This tool allows you to insert debug cores into your design, which can then be used to capture and analyze signals in real-time.

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XC6SLX25-2FGG484I Overview

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Image Part Number Model
Part Image XC6SLX25-2FGG484I AMD Xilinx

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FGG484C AMD Xilinx

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FG484I AMD

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FG484C AMD

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FG484I AMD Xilinx

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

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