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XC6SLX75T-2FGG484I - AMD

Description: FPGA - Field Programmable Gate Array XC6SLX75T-2FGG484I

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XC6SLX75T-2FGG484I Details

  • Manufacturer Part Number:

    XC6SLX75T-2FGG484I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    12 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    4

  • Clock Frequency-Max:

    667 MHz

  • Combinatorial Delay of a CLB-Max:

    0.26 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    5831

  • Number of Inputs:

    268

  • Number of Logic Cells:

    74637

  • Number of Outputs:

    268

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    5831 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 40 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    23 mm

XC6SLX75T-2FGG484I Frequently Asked Questions (FAQs)

  • The maximum operating frequency is 350 MHz, but it depends on the specific application and design.
  • You can use the MIG (Memory Interface Generator) tool from Xilinx to generate a DDR3 memory interface. The tool provides a customized IP core for the FPGA.
  • The power consumption varies depending on the design and usage. However, the typical power consumption is around 1.2W to 2.5W, according to the datasheet.
  • Yes, the XC6SLX75T-2FGG484I supports high-speed serial interfaces like PCIe Gen2 and SATA II. You can use the FPGA's GTX transceivers to implement these interfaces.
  • You can use Xilinx's ISE Design Suite or Vivado Design Suite to program and debug the FPGA. These tools provide a comprehensive development environment for designing, implementing, and testing your FPGA design.

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XC6SLX75T-2FGG484I Overview

Use the download button to access the XC6SLX75T-2FGG484I 3D model. You can still request or build the schematic symbol and PCB footprint by using the respective build or request forms on this page.
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Image Part Number Model
Part Image XC6SLX75T-2FGG484I AMD Xilinx

Field Programmable Gate Array, 5831 CLBs, 667MHz, 74637-Cell, CMOS, PBGA484

Part Image XC6SLX75T-2FG484C AMD

Field Programmable Gate Array, 5831 CLBs, 667MHz, 74637-Cell, CMOS, PBGA484

Part Image XC6SLX75T-2FG484C AMD Xilinx

Field Programmable Gate Array, 5831 CLBs, 667MHz, 74637-Cell, CMOS, PBGA484

Part Image XC6SLX75T-2FGG484C AMD Xilinx

Field Programmable Gate Array, 5831 CLBs, 667MHz, 74637-Cell, CMOS, PBGA484