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XCVU13P-2FHGB2104I - AMD

Description: IC FPGA 702 I/O 2104FCBGA

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XCVU13P-2FHGB2104I - AMD - PCB symbol
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PCB Footprints
XCVU13P-2FHGB2104I - AMD PCB footprint - BGA - BGA - FHGB2104I
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XCVU13P-2FHGB2104I - AMD - 3D model - BGA - FHGB2104I
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XCVU13P-2FHGB2104I Details

  • Manufacturer Part Number:

    XCVU13P-2FHGB2104I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    BGA-2104

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    20 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    10

  • JESD-30 Code:

    S-PBGA-B2104

  • Length:

    52.5 mm

  • Number of CLBs:

    216000

  • Number of Inputs:

    832

  • Number of Logic Cells:

    3780000

  • Number of Outputs:

    832

  • Number of Terminals:

    2104

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    216000 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA2104,46X46,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    4.32 mm

  • Supply Voltage-Max:

    0.876 V

  • Supply Voltage-Min:

    0.825 V

  • Supply Voltage-Nom:

    0.85 V

  • Surface Mount:

    YES

  • Technology:

    16 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    52.5 mm

XCVU13P-2FHGB2104I Frequently Asked Questions (FAQs)

  • The maximum power consumption of the XCVU13P-2FHGB2104I is approximately 25W, but this can vary depending on the specific application and usage.
  • To implement a DDR4 memory interface on the XCVU13P-2FHGB2104I, you need to use the MIG (Memory Interface Generator) IP core provided by AMD, which generates a customized DDR4 controller based on your specific requirements.
  • The maximum clock frequency supported by the XCVU13P-2FHGB2104I is 500 MHz, but this can vary depending on the specific clock domain and the quality of the clock signal.
  • To optimize power consumption on the XCVU13P-2FHGB2104I, you can use various techniques such as clock gating, voltage scaling, and dynamic voltage and frequency scaling (DVFS), as well as using the AMD-provided power optimization tools and IP cores.
  • The maximum bandwidth of the PCIe interface on the XCVU13P-2FHGB2104I is 16 GT/s, which corresponds to a bandwidth of 985 MB/s per lane, with a maximum of 16 lanes.

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XCVU13P-2FHGB2104I Overview

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Part Image XCVU13P-2FHGB2104E AMD

Field Programmable Gate Array, 216000 CLBS, 3780000-Cell, PBGA2104