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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	6116SA20SOG Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Small Outline Packages	6116SA20SOG	3D model not available Symbol and footprint available 2	1 Download Model
	71T75802S166BGGI8 Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	BGA	71T75802S166BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	5962-8866205XA Renesas Electronics	1	The 5962-88662 (71256 SRAM) is organized as 32K x 8. This part offers a reduced power standby mode for significant system level power and cooling savings. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Ceramic Dual-In-Line Packages	5962-8866205XA	3D model not available Symbol and footprint available 2	1 Download Model
	71V3577S75BQ Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V3577S75BQ	3D model available Symbol and footprint available 3	1 Download Model

	5962-3829414MZA Renesas Electronics	1	The 5962-38294 (7164 SRAM) is organized as 8K x 8 and offers a reduced power standby mode. The low-power version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation.	Ceramic Dual-In-Line Packages	5962-3829414MZA	3D model not available Symbol and footprint available 2	1 Download Model
	71V3577S75PFG Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V3577S75PFG	3D model available Symbol and footprint available 3	1 Download Model
	7133SA25G Renesas Electronics	1	The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7133SA25G	3D model available Symbol and footprint available 3	1 Download Model
	70V9289L7PFG Renesas Electronics	1	The 70V9289 is a high-speed 64K x 16-bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V9289L7PFG	3D model available Symbol and footprint available 3	1 Download Model
	70V9269S12PRFGI Renesas Electronics	1	The 70V9269 is a high-speed 16K x 16 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V9269S12PRFGI	3D model available Symbol and footprint available 3	1 Download Model
	6116LA45DB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Dual-In-Line Packages	6116LA45DB	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S85BQ8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67703S85BQ8	3D model available Symbol and footprint available 3	1 Download Model
	70V631S12BFI Renesas Electronics	1	The 70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V631S12BFI	3D model available Symbol and footprint available 3	1 Download Model
	71V3557S75BGG8 Renesas Electronics	1	The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	BGA	71V3557S75BGG8	3D model available Symbol and footprint available 3	1 Download Model
	6116SA70DB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Dual-In-Line Packages	6116SA70DB	3D model available Symbol and footprint available 3	1 Download Model
	70261L20PFGI Renesas Electronics	1	The 70261 is a high-speed 16K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70261L20PFGI	3D model available Symbol and footprint available 3	1 Download Model

	7006L20JGI Renesas Electronics	1	The 7006 is a high-speed 16K x 8 Dual-Port Static RAM designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Plastic Leaded Chip Carrier	7006L20JGI	3D model available Symbol and footprint available 3	1 Download Model
	6116SA70TDB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	6116SA70TDB	3D model not available Symbol and footprint available 2	1 Download Model
	6116SA25SOGI Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Small Outline Packages	6116SA25SOGI	3D model not available Symbol and footprint available 2	1 Download Model
	70T3589S133BFI8 Renesas Electronics	1	The 70T3589 is a high-speed 64K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3589 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3589S133BFI8	3D model available Symbol and footprint available 3	1 Download Model
	6116LA150TDB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	6116LA150TDB	3D model not available Symbol and footprint available 2	1 Download Model
	71V3559S85BQG8 Renesas Electronics	1	The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	BGA	71V3559S85BQG8	3D model available Symbol and footprint available 3	1 Download Model
	6116SA45TDB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	6116SA45TDB	3D model not available Symbol and footprint available 2	1 Download Model
	N64S830HAS22I onsemi	1	2.7 to 3.6 V power supply range; Very low standby current - as low as 1 uA; Very low operating current - as low as 3 mA; Flexible operating modes: word read and write, page mode (32 word page), and burst mode (full array); 8 K x 8 bit organization ; Simple memory control: single chip select (CS), serial input (SI) and serial output (SO); Self timed write cycles; Built-in write protection (CS high); HOLD pin for pausing communication; High reliability - unlimited write cycles; RoHS Compliant Packages - Green	Small Outline Packages	N64S830HAS22I	3D model available Symbol and footprint available 3	1 Download Model
	RMQS2A3636DGBA-332#AC0 Renesas Electronics	1	The RMQS2A3636DGBA is a 1, 048, 576-word by 36-bit and the RMQS2A3618DGBA is a 2, 097, 152-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Sp	BGA	RMQS2A3636DGBA-332#AC0	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S85PFG Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65703S85PFG	3D model available Symbol and footprint available 3	1 Download Model
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