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CD4024BDMSR
Renesas Electronics
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1 | The CD4020BMS (14-stage), CD4024BMS (7-stage), and CD4040BMS (12-stage) are ripple carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and CD4040BMS are supplied in these 14-lead ou | Dual-In-Line Packages | CD4024BDMSR |
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MC14017BDG
onsemi
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1 | Pin-for-Pin Replacement for CD4017B; Fully Static Operation; Divide-by-N Counting; Carry Out Output for Cascading; Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range; Supply Voltage Range = 3.0 Vdc to 18 Vdc; DC Clock Input Circuit Allows Slow Rise Times; Triple Diode Protection on All Inputs; Pb-Free Packages are Available* | Small Outline Packages | MC14017BDG |
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HCC4024BDT
STMicroelectronics
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1 | Rad-hard, high voltage, CMOS logic series DIL 14FP | Ceramic Dual-In-Line Packages | HCC4024BDT |
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74AHC1G4208GW-Q10H
Nexperia
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1 | Counter IC Divide-by-2 1 Element 8 Bit Negative Edge 5-TSSOP 5.5V 100 mA -40 °C to +125 °C | SOT23 (5-Pin) | 74AHC1G4208GW-Q10H |
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TC74VHC161FK
Toshiba
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1 | 4-bit Binary Counter, US16 | Small Outline Packages | TC74VHC161FK |
3
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HCC4516BDG
STMicroelectronics
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1 | Rad-hard presettable 4-bit binary up/down counter | Ceramic Dual-In-Line Packages | HCC4516BDG |
3
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74HC193PW,112
Nexperia
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1 | 74HC(T)193 - Presettable synchronous 4-bit binary up, down counter@en-us | Small Outline Packages | 74HC193PW,112 |
3
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74LV393D-Q100J
Nexperia
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1 | 74LV393-Q100 - Dual 4-bit binary ripple counter@en-us | Small Outline Packages | 74LV393D-Q100J |
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74LVC161DB,118
Nexperia
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1 | 74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset@en-us | Small Outline Packages | 74LVC161DB,118 |
3
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74HC393D,652
Nexperia
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1 | 74HC(T)393 - Dual 4-bit binary ripple counter@en-us | Small Outline Packages | 74HC393D,652 |
3
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HCC4520BDT
STMicroelectronics
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1 | Rad-hard, high voltage, CMOS logic series | Ceramic Dual-In-Line Packages | HCC4520BDT |
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74HC4040D-Q100J
Nexperia
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1 | 74HC(T)4040-Q100 - 12-stage binary ripple counter@en-us | Other | 74HC4040D-Q100J |
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74HC4024D
Nexperia
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1 | 7-stage binary ripple counter | Small Outline Packages | 74HC4024D |
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MC74HC390ADG
onsemi
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1 | In Compliance with the Requirements Defined by JEDEC Standard No 7A; High Noise Immunity Characteristic of CMOS Devices; Operating Voltage Range: 2 to 6 V; Low Input Current: 1 mA; Chip Complexity: 244 FETs or 61 Equivalent Gates; Output Drive Capability: 10 LSTTL Loads; Outputs Directly Interface to CMOS, NMOS, and TTL; Pb-Free Packages are Available* | Small Outline Packages | MC74HC390ADG |
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TC74HC4060AP
Toshiba
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1 | 14-Stage Binary Counter, DIP16, High speed: fmax = 58 MHz (typ.) at VCC = 5 V | Dual-In-Line Packages | TC74HC4060AP |
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74LV4060DB,118
Nexperia
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1 | 74LV4060 - 14-stage binary ripple counter with oscillator@en-us | Small Outline Packages | 74LV4060DB,118 |
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CD40193BKMSR
Renesas Electronics
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1 | CD40192BMS presettable BCD up/down counter and the CD40193BMS presettable binary up/down counter each consist of four synchronously clocked, gated D type flip-flops connected as a counter. The inputs consist of four individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals, and a master RESET. Four buffered Q signal outputs as well as CARRY and BORROW outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a h | Small Outline Packages | CD40193BKMSR |
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HCC40103BDT
STMicroelectronics
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1 | Rad-hard dual binary up-down counter | Ceramic Dual-In-Line Packages | HCC40103BDT |
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MC74HC161ADG
onsemi
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1 | Low Input Current: 1.0 mA; Operating Voltage Range: 2.0 to 6.0 V; Outputs Directly Interface to CMOS, NMOS, and TTL; Output Drive Capability: 10 LSTTL Loads; High Noise Immunity Characteristic of CMOS Devices; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 192 FETs or 48 Equivalent Gates; Pb-Free Packages are Available* | Small Outline Packages | MC74HC161ADG |
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HEF4520BT,652
Nexperia
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1 | HEF4520B - Dual binary counter@en-us | Other | HEF4520BT,652 |
3
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74LV393D,112
Nexperia
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1 | 74LV393 - Dual 4-bit binary ripple counter@en-us | Small Outline Packages | 74LV393D,112 |
3
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74LV393D,118
Nexperia
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1 | 74LV393 - Dual 4-bit binary ripple counter@en-us | Other | 74LV393D,118 |
3
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HCF4020BEY
STMicroelectronics
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1 | Counter IC Binary Counter 1 Element 14 Bit Negative Edge 16-DIP | Dual-In-Line Packages | HCF4020BEY |
3
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SN74AS161N
Texas Instruments
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1 | SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS | Dual-In-Line Packages | SN74AS161N |
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SN74LS593DW
Texas Instruments
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1 | Texas Instruments SN74LS593DW, 8-stage, Binary Counter/Register, Up Counter, 5V, 20-Pin SOIC | Other | SN74LS593DW |
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