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7204L30DB
Renesas Electronics
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1 | The 7204 is a 4K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Ceramic Dual-In-Line Packages | 7204L30DB |
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72841L10TFG8
Renesas Electronics
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1 | The 72841 is a 4K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72841 architecture lends itself to many flexible configurations s | Quad Flat Packages | 72841L10TFG8 |
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72V273L7-5BCGI8
Renesas Electronics
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1 | The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | BGA | 72V273L7-5BCGI8 |
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72V241L10PFG8
Renesas Electronics
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1 | The 72V241 is a 4K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72241 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. | Quad Flat Packages | 72V241L10PFG8 |
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72T18115L5BBI
Renesas Electronics
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1 | The 72T18115 is a 256K x 18 / 512K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode. | BGA | 72T18115L5BBI |
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72V3680L6BB8
Renesas Electronics
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1 | The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. | BGA | 72V3680L6BB8 |
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72V3680L6PFG
Renesas Electronics
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1 | The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. | Quad Flat Packages | 72V3680L6PFG |
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7203L40DB
Renesas Electronics
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1 | The 7203 is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Ceramic Dual-In-Line Packages | 7203L40DB |
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74HC40105D,652
Nexperia
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1 | 74HC40105 - 4-bit x 16-word FIFO register@en-us | Small Outline Packages | 74HC40105D,652 |
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72V2103L6PFG8
Renesas Electronics
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1 | The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | Quad Flat Packages | 72V2103L6PFG8 |
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72V04L25JGI
Renesas Electronics
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1 | IC FIFO ASYNC 4KX9 25NS 32PLCC | Plastic Leaded Chip Carrier | 72V04L25JGI |
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72V06L15JG8
Renesas Electronics
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1 | The 72V06 is a 16K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Plastic Leaded Chip Carrier | 72V06L15JG8 |
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72V251L15JGI8
Renesas Electronics
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1 | The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. | Plastic Leaded Chip Carrier | 72V251L15JGI8 |
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72V06L25JGI8
Renesas Electronics
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1 | The 72V06 is a 16K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Plastic Leaded Chip Carrier | 72V06L25JGI8 |
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7201LA12PDG
Renesas Electronics
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1 | The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Ceramic Dual-In-Line Packages | 7201LA12PDG |
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AT24C01D-MAHM-T
Microchip
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1 | EEPROM Serial-2Wire 1K-bit 128 x 8 1.8V/2.5V/3.3V 8-Pin UDFN EP T/R | Small Outline No-lead | AT24C01D-MAHM-T |
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93C46B-I/P
Microchip
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1 | Microchip 93C46B-I/P Serial EEPROM Memory, 1kbit, 200ns, 4.5 → 5.5 V 8-Pin PDIP | Dual-In-Line Packages | 93C46B-I/P |
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AT24C04D-PUM
Microchip
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1 | MICROCHIP - AT24C04D-PUM - EEPROM, 4 Kbit, 512K x 8bit, Serial I2C (2-Wire), 1 MHz, DIP, 8 Pins | Dual-In-Line Packages | AT24C04D-PUM |
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25LC256T-E/ST
Microchip
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1 | • Maximum Clock 10 MHz• Low-Power CMOS Technology:- Maximum Write current: 5 mA at 5.5V,10 MHz- Read current: 6 mA at 5.5V, 10 MHz- Standby current: 1 µA at 5.5V• 32,768 x 8-Bit Organization• 64-Byte Page• Self-Timed Erase and Write Cycles (5 msmaximum)• Block Write Protection:- Protect none, 1/4, 1/2 or all of array• Built-In Write Protection:- Power-on/off data protection circuitry- Write enable latch- Write-protect pin• Sequential Read• High Reliability:- Endurance: 1, | Small Outline Packages | 25LC256T-E/ST |
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24LC128-I/SM
Microchip
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1 | 128K,16K X 8,2.5V Serial EE,SOIC-8 | Small Outline Packages | 24LC128-I/SM |
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BR24G04NUX-3TTR
ROHM Semiconductor
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1 | ROHM - BR24G04NUX-3TTR - SERIAL EEPROM, 4KBIT, 400KHZ, VSON-8 | Small Outline No-lead | BR24G04NUX-3TTR |
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BR24G256-3
ROHM Semiconductor
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1 | EEPROM Zener Diode, 100mW, 2 Pin. | Dual-In-Line Packages | BR24G256-3 |
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M93C46-WMN6
STMicroelectronics
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1 | M93C46-WMN6, Serial EEPROM Memory 1kbit, Serial-Microwire 2.5 → 5.5 V, 8-Pin SOIC | Small Outline Packages | M93C46-WMN6 |
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25AA1024T-I/MF
Microchip
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1 | EEPROM 128kx8 - 1.8V | Small Outline No-lead | 25AA1024T-I/MF |
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24AA256UID-I/ST
Microchip
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1 | 256K EEPROM Serial-I2C 32Kx8 1.8V TSSOP8 Microchip 24AA256UID-I/ST Serial EEPROM Memory, 256kbit, 1000ns, 1.7 → 5.5 V 8-Pin TSSOP | Small Outline Packages | 24AA256UID-I/ST |
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