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| Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action |
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232-364
Wago
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1 | THT male header for double-deck assembly; 1.0 x 1.0 mm solder pin; angled; Pin spacing 5.08 mm; 4-pole | Other | 232-364 |
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236-410
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 10-pole; CAGE CLAMP®; commoning option | Other | 236-410 |
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832-3643
Wago
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1 | THT male header; 1.2 x 1.2 mm solder pin; angled; 100% protected against mismating; Silver-plated contacts; Pin spacing 10.16 mm; 3-pole | Other | 832-3643 |
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 4-pole; suitable for Ex-e applications; CAGE CLAMP®; commoning option | Other | 236-404/332-009/999-950 |
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236-401/332-000
Wago
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1 | Stackable PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 1-pole; CAGE CLAMP®; commoning option | Other | 236-401/332-000 |
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09023646921
HARTING
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1 | DIN B male angled 64pin, w/ board locks, PL2 | Other | 09023646921 |
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M20-7823646
Harwin
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1 | M20: 36 Pos Receptacle SIL Straight 3mm THT Connector 8.5mm high Tin | Other | M20-7823646 |
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723642L15PFG
Renesas Electronics
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1 | The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. | Quad Flat Packages | 723642L15PFG |
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723642L15PFG8
Renesas Electronics
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1 | The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. | Quad Flat Packages | 723642L15PFG8 |
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723646L12PF8
Renesas Electronics
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1 | The 723646 is a 1K x 36 x 2 Triple Bus sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. FIFO data can be read out and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. The clocks for each port are independent of one another and can be asynchronous or coincident. Communication between each port may bypass the FIFOs via two mailbox registers. These devices can operate in the IDT Standard mode or First Wo | Quad Flat Packages | 723646L12PF8 |
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723641L20PF
Renesas Electronics
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1 | The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals. | Quad Flat Packages | 723641L20PF |
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723643L15PF8
Renesas Electronics
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1 | The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. | Quad Flat Packages | 723643L15PF8 |
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723642L12PF
Renesas Electronics
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1 | The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. | Quad Flat Packages | 723642L12PF |
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SL622364GECO
Fischer Elektronik GmbH & Co. KG
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1 | male header | Other | SL622364GECO |
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2364427-1
TE Connectivity
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1 | Board-to-Board, 36 Position, 1 mm [.04 in] Centerline, Vertical, Black, 11.25 mm [.44 in] Height, 8.2 mm [.32 in] Width, PCI & PCI Express Connectors | Other | 2364427-1 |
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OPA2364AID
Texas Instruments
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1 | 1.8V, High CMR, RRIO Op Amp | Small Outline Packages | OPA2364AID |
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TS5A22364YZPR
Texas Instruments
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1 | 0.65-Ω Dual SPDT Analog Switch With Negative Rail Capability | BGA | TS5A22364YZPR |
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TS5A22364QDGSRQ1
Texas Instruments
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1 | Automotive 0.65-Ω Dual SPDT Analog Switch With Negative Signaling Capability | Small Outline Packages | TS5A22364QDGSRQ1 |
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LTC2364CMS-16#PBF
Analog Devices
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1 | Analog to Digital Converters - ADC 16-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 94.7dB SNR | Small Outline Packages | LTC2364CMS-16#PBF |
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236-416
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 16-pole; CAGE CLAMP®; commoning option | Other | 236-416 |
3
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1 | THR PCB terminal block; 2.5 mm²; Pin spacing 5 mm; 6-pole; CAGE CLAMP®; in tape-and-reel packaging; commoning option | Other | 236-406/334-604/997-406 |
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236-402/334-604
Wago
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1 | THR PCB terminal block; 2.5 mm²; Pin spacing 5 mm; 2-pole; CAGE CLAMP®; commoning option | Other | 236-402/334-604 |
3
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236-406/334-023
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 6-pole; CAGE CLAMP®; commoning option | Other | 236-406/334-023 |
3
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 3-pole; suitable for Ex-e applications; CAGE CLAMP®; commoning option | Other | 236-403/332-009/999-950 |
3
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236-413
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 13-pole; CAGE CLAMP®; commoning option | Other | 236-413 |
3
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