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Image Part Number D.S Description Package Category Prices / Stock Model Action
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723656L15PF8 Renesas Electronics
1 The 723656 is a 2K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723656L15PF8 1 Download Model
Part Image Part Image 1 Low Power Programmable Oscillator, 3.2 x 2.5 x 0.75 mm Package Other SIT8008BC-23-28E-3.656000 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-G-S 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-FM-S 1 Download Model
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SL143656Z Fischer Elektronik GmbH & Co. KG
1 male header Other SL143656Z 1 Download Model
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72V3656L15PF Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L15PF 1 Download Model
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SLVW403656Z Fischer Elektronik GmbH & Co. KG
1 Dual Row, Male, Pitch 1.27 x 1.27 mm, THT, 56 Position Other SLVW403656Z 1 Download Model
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1436563 Phoenix Contact
1 SACC-DSIV-FS-5CON-L90 SCO - Device connector rear mounting, 5-position, Socket, angled, M12-SPEEDCON, A-coding, THR and wave soldering, this item is expected to be lead-free from Q2 2026 in accordance with RoHS II without exception 6c (Pb < 0.1%), a lead-free alternative is possible on request in advance Other 1436563 1 Download Model
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72V3656L10PFI Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L10PFI 1 Download Model
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SLY8SMD03656G Fischer Elektronik GmbH & Co. KG
This part was updated within the past 30 days.
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1 Dual Row, SMD, Male, Pitch 2 x 2mm, 56 Position Other SLY8SMD03656G 1 Download Model
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SL1436568GECO Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436568GECO 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-TM-S 1 Download Model
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SLVW203656Z Fischer Elektronik GmbH & Co. KG
1 Dual Row, Male, Pitch 1.27 x 2.54 mm; suitable for female header BLM, THT, 56 Position Other SLVW203656Z 1 Download Model
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1036560000 Weidmüller
1 PCB connector (board connection), 160 V, 17.5 A, Pitch in mm: 3.81, Number of poles: 9, THT/THR solder connection, Box Other 1036560000 1 Download Model
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SLVW5SMD03656G Fischer Elektronik GmbH & Co. KG
This part was updated within the past 30 days.
Set alerts for model updates on the part download page.
1 Dual Row, SMD, Male, Pitch 1.27 x 1.27mm, 56 Position Other SLVW5SMD03656G 1 Download Model
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SL1436560GECO Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436560GECO 1 Download Model
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723656L15PF Renesas Electronics
1 The 723656 is a 2K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723656L15PF 1 Download Model
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SL1436566Z Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436566Z 1 Download Model
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SL1436562G Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436562G 1 Download Model
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SL1436564G Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436564G 1 Download Model
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SL1436568G Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436568G 1 Download Model
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SL1436560Z Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436560Z 1 Download Model
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SL133656Z Fischer Elektronik GmbH & Co. KG
1 male header Other SL133656Z 1 Download Model
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2336568-4 TE Connectivity
1 RECEPT ASSY, RA, 168 POS, SLIVER 2.0 Other 2336568-4 1 Download Model
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SL1436562Z Fischer Elektronik GmbH & Co. KG
1 male header Other SL1436562Z 1 Download Model
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