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72825LB15PFGI8
Renesas Electronics
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1 | The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for | Quad Flat Packages | 72825LB15PFGI8 |
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CA4-7.3728-20-3050-R
Aker Technology
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1 | Crystal,12.7mm x4.5mm,7.3728MHz,20pF.-20-70C | Other | CA4-7.3728-20-3050-R |
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72825LB15BGG
Renesas Electronics
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1 | The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for | BGA | 72825LB15BGG |
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TPM27282-SO1R
3Peak Incorporated
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1 | High Precision Operational Amplifier | Small Outline Packages | TPM27282-SO1R |
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690367282476
Würth Elektronik
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1 | WR-MM Female SMT Connector with Polarization without Latch, 24 pins, SMT, straight | Other | 690367282476 |
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PF2472-82RF1
Bourns
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1 | PF2472 82 OHM 1% | Other | PF2472-82RF1 |
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C2220H362JGGAF7282
Yageo Group
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1 | SMD, MLCC, High Temperature, Ultra-Stable, Low Loss | Other | C2220H362JGGAF7282 |
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C1210H104J5GAF7282
Yageo Group
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1 | SMD, MLCC, High Temperature, Ultra-Stable, Low Loss | Other | C1210H104J5GAF7282 |
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C0603H102J5GAE7282
Yageo Group
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1 | SMD, MLCC, High Temperature, Ultra-Stable, Low Loss | Other | C0603H102J5GAE7282 |
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C0603H103J3GAE7282
Yageo Group
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1 | SMD Indust C0G HT200C, Ceramic, 0.01 uF, 5%, 25 VDC, 62.5 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 3.7 mg, 0603, 1.6mm, 0.8mm, 0.8mm, 0.7mm, 0.35mm, 368, 26 Weeks, 120 | Other | C0603H103J3GAE7282 |
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72821L25TF
Renesas Electronics
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1 | The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s | Quad Flat Packages | 72821L25TF |
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BD7282YFJ-CE2
ROHM Semiconductor
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1 | High Speed Operational Amplifiers Nano Cap, Automotive Low Noise & Rail-to-Rail Input/Output High Speed CMOS Operational Amplifiers | Small Outline Packages | BD7282YFJ-CE2 |
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UCC27282QDRQ1
Texas Instruments
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1 | Gate Drivers Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable 8-SOIC -40 to 125 | Small Outline Packages | UCC27282QDRQ1 |
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ADV7282WBCPZ
Analog Devices
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1 | Video ICs 10-bit SD Diff Video Decoder w/ I2P Out | Quad Flat No-Lead | ADV7282WBCPZ |
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UCC27282QDQ1
Texas Instruments
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1 | Gate Drivers Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable 8-SOIC -40 to 125 | Small Outline Packages | UCC27282QDQ1 |
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UCC27282QDRCTQ1
Texas Instruments
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1 | Gate Drivers Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable 10-VSON -40 to 125 | Other | UCC27282QDRCTQ1 |
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72825LB15PFGI
Renesas Electronics
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1 | The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for | Quad Flat Packages | 72825LB15PFGI |
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ADV7282AWBCPZ-M
Analog Devices
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1 | Video ICs 10-bit SD Diff Video Decoder | Quad Flat No-Lead | ADV7282AWBCPZ-M |
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ADV7282AWBCPZ-RL
Analog Devices
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1 | 10-Bit, 4× Oversampled SDTV Video Decoder with Differential Inputs | Quad Flat No-Lead | ADV7282AWBCPZ-RL |
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TPM27282-DF8R
3Peak Incorporated
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1 | 120-V Supply, 3.5-A Peak, High-frequency HS and LS Gate Driver | Small Outline No-lead | TPM27282-DF8R |
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72821L25TFI8
Renesas Electronics
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1 | The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s | Quad Flat Packages | 72821L25TFI8 |
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AS-7.3728-20-EXT-SMD-TR
RALTRON
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1 | MHz Crystal, 7.3728 MHz, 13.5 x 4.8 mm, ±30 ppm tolerance, ±50 ppm stability, 20 pF, -40~85°C, SMD | Other | AS-7.3728-20-EXT-SMD-TR |
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72821L10TF8
Renesas Electronics
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1 | The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s | Quad Flat Packages | 72821L10TF8 |
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72821L15PF
Renesas Electronics
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1 | The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s | Quad Flat Packages | 72821L15PF |
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C0603H222F5GAE7282
Yageo Group
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1 | SMD, MLCC, High Temperature, Ultra-Stable, Low Loss | Other | C0603H222F5GAE7282 |
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