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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	CY62126EV30LL-45ZSXI Infineon	1	Cypress Semiconductor CY62126EV30LL-45ZSXI SRAM Memory, 1Mbit, 2.2 → 3.6 V, 45ns 44-Pin TSOP	Small Outline Packages	CY62126EV30LL-45ZSXI	3D model available Symbol and footprint available 3	1 Download Model
	IS66WVO8M8DBLL-166BLI Integrated Silicon Solution Inc.	1	SRAM 64Mb 1.8V/3.0V SERIAL PSRAM MEMORY WITH 200MHZ DTR OPI (OCTAL PERIPHERAL INTERFACE) PROTOCOL	BGA	IS66WVO8M8DBLL-166BLI	3D model available Symbol and footprint available 3	1 Download Model
	IS61WV20488FBLL-8BLI Integrated Silicon Solution Inc.	1	SRAM 16Mb,High-Speed,Async,2Mbx8,8ns, 2.4v-3.6v, 48 Ball mBGA (6x8 mm), RoHS	BGA	IS61WV20488FBLL-8BLI	3D model available Symbol and footprint available 3	1 Download Model
	IS66WVE4M16EBLL-70BLI-TR Integrated Silicon Solution Inc.	1	Asynchronous and page mode interface Dual voltage rails for optional performance ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V Page mode read access Interpage Read access : 60ns, 70ns Intrapage Read access : 25ns Low Power Consumption Asynchronous Operation < 30 mA Intrapage Read < 23mA Standby < 200 uA (max.) at -40°C~85°C Deep power-down (DPD) ALL/CLL: < 3µA (Typ) BLL: < 10µA (Typ)	BGA	IS66WVE4M16EBLL-70BLI-TR	3D model available Symbol and footprint available 3	1 Download Model

	5962-8861011ZA Renesas Electronics	1	The 5962-88610 (IDT 7133/43) is a high-speed 2K x 16 Dual-Port Static RAMs. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Military grade product in compliance with MIL-PRF-38535 QML.	Other	5962-8861011ZA	3D model available Symbol and footprint available 3	1 Download Model
	71V416L10BE Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L10BE	3D model available Symbol and footprint available 3	1 Download Model
	71124S20YGI Renesas Electronics	1	The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71124S20YGI	3D model not available Symbol and footprint available 2	1 Download Model
	70T651S12BCI8 Renesas Electronics	1	The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T651S12BCI8	3D model available Symbol and footprint available 3	1 Download Model
	70T3339S166BC8 Renesas Electronics	1	The 70T3339 is a high-speed 512K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3339 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3339S166BC8	3D model available Symbol and footprint available 3	1 Download Model
	5962-8861010ZA Renesas Electronics	1	The 5962-88610 (IDT 7133/43) is a high-speed 2K x 16 Dual-Port Static RAMs. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Military grade product in compliance with MIL-PRF-38535 QML.	Other	5962-8861010ZA	3D model available Symbol and footprint available 3	1 Download Model
	5962-8866516ZA Renesas Electronics	1	The 5962-88665 (IDT 7133/43) high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power offers battery backup data retention capability, with each port typically consuming 200?W for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML.	Other	5962-8866516ZA	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S75BQG Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65703S75BQG	3D model available Symbol and footprint available 3	1 Download Model
	71124S20YG8 Renesas Electronics	1	The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71124S20YG8	3D model available Symbol and footprint available 3	1 Download Model
	71V67602S150PFGI8 Renesas Electronics	1	The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67602S150PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA10YG8 Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71V124SA10YG8	3D model available Symbol and footprint available 3	1 Download Model

	R1LV1616HSA-4SI#B1 Renesas Electronics	1	The R1LV1616HSA-I Series is 16-Mbit static RAM organized 1-Mword × 16-bit / 2-Mword × 8-bit with embedded ECC. R1LV1616HSA-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-pin plastic TSOPI for high density surface mounting.	Small Outline Packages	R1LV1616HSA-4SI#B1	3D model available Symbol and footprint available 3	1 Download Model
	HM1-65642-9 Renesas Electronics	1	The HM-65642 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The HM-65642 is a full CMOS RAM which utilizes an array of six tr	Ceramic Dual-In-Line Packages	HM1-65642-9	3D model not available Symbol and footprint available 2	1 Download Model
	70T653MS12BCI Renesas Electronics	1	The 70T653M is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone 18874K-bit Dual-Port RAM. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T653MS12BCI	3D model available Symbol and footprint available 3	1 Download Model
	70V7339S166BFG8 Renesas Electronics	1	The 70V7339 is a high-speed 512K x 18 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 8K x 18 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 8K x 18 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7339S166BFG8	3D model available Symbol and footprint available 3	1 Download Model
	71T75602S166PFG8 Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	Quad Flat Packages	71T75602S166PFG8	3D model available Symbol and footprint available 3	1 Download Model
	7134LA20PDG Renesas Electronics	1	The 7134 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade prod	Dual-In-Line Packages	7134LA20PDG	3D model available Symbol and footprint available 3	1 Download Model
	71T75802S200BGG8 Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	BGA	71T75802S200BGG8	3D model available Symbol and footprint available 3	1 Download Model
	5962-8866203XA Renesas Electronics	1	The 5962-88662 (71256 SRAM) is organized as 32K x 8. This part offers a reduced power standby mode for significant system level power and cooling savings. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Ceramic Dual-In-Line Packages	5962-8866203XA	3D model not available Symbol and footprint available 2	1 Download Model
	70V7519S133BF Renesas Electronics	1	The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7519S133BF	3D model available Symbol and footprint available 3	1 Download Model
	70V7339S166BFG Renesas Electronics	1	The 70V7339 is a high-speed 512K x 18 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 8K x 18 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 8K x 18 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7339S166BFG	3D model available Symbol and footprint available 3	1 Download Model
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