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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V831L10TFG8 Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V221L15PFG8 Renesas Electronics	1	The 72V221 is a 1K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72221 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V221L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	5962-8866905YA Renesas Electronics	1	The 5962-88669 (IDT 7203) is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	5962-8866905YA	3D model not available Symbol and footprint available 2	1 Download Model
	72T36125L5BB Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L5BB	3D model available Symbol and footprint available 3	1 Download Model

	72V36100L6PFG8 Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L6PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T1875L4-4BB Renesas Electronics	1	The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1875L4-4BB	3D model available Symbol and footprint available 3	1 Download Model
	72T1865L6-7BB Renesas Electronics	1	The 72T1865 is a 8K x 18 / 16K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1865L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72T1885L5BBI Renesas Electronics	1	The 72T1885 is a 32K x 18 / 64K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1885L5BBI	3D model available Symbol and footprint available 3	1 Download Model
	72V841L15TFGI8 Renesas Electronics	1	The 72V841is a 4K x 9 dual synchronous FIFO that is functionally equivalent to two 72V241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V841L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	723632L15PFG8 Renesas Electronics	1	The 723632 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 512 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723632L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V283L7-5PFGI Renesas Electronics	1	The 72V283 64K x 9/32K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V283L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72285L10TFG Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L6PFG Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3690L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T1875L5BB Renesas Electronics	1	The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1875L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V231L10PFG Renesas Electronics	1	The 72V231 is a 2K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72231 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V231L10PFG	3D model available Symbol and footprint available 3	1 Download Model

	72125L25SOG8 Renesas Electronics	1	The 72125 is a 1K x 16 dedicated, parallel-to-serial FIFOs. The ability to buffer wide word widths (x16) make this FIFO ideal for laser printers, FAX machines, local area networks (LANS), video storage and disk/tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT's unique serial expansion logic makes this possible using a minimum of pins.	Small Outline Packages	72125L25SOG8	3D model available Symbol and footprint available 3	1 Download Model
	72271LA10PFG Renesas Electronics	1	The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperS	Quad Flat Packages	72271LA10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3660L6BB8 Renesas Electronics	1	The 72V3660 4K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3660L6BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V241L15PFGI Renesas Electronics	1	The 72V241 is a 4K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72241 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V241L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	7202LA12TPG Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7202LA12TPG	3D model available Symbol and footprint available 3	1 Download Model
	7201LA20DB Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7201LA20DB	3D model not available Symbol and footprint available 2	1 Download Model
	72V235L10TFG Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V245L10PFG Renesas Electronics	1	The 72V245 is a 4K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72245 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V245L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V243L6PFG8 Renesas Electronics	1	The 72V243 4K x 9/2K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V243L6PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V291L10TFG8 Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
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