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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V36110L15PF Renesas Electronics	1	The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36110L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72413L25SOG8 Renesas Electronics	1	The 72413 is a 64 x 5, high-speed First-In/First-Out memory. It is expandable in bit width. All speed versions are cascadable in depth. It is ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers.	Small Outline Packages	72413L25SOG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L10PF Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3690L10PF	3D model available Symbol and footprint available 3	1 Download Model
	AT45DB081E-MHN-T Renesas Electronics	1	The AT45DB081E DataFlash is a member of our System Enhancing class of code and data storage solutions designed with an advanced dual SRAM buffer architecture that makes it the most efficient memory for data logging. It also incorporates a suite of advanced features that save system power, reduce processor overhead, simplify software development, and provide comprehensive data security and integrity options.	Small Outline No-lead	AT45DB081E-MHN-T	3D model available Symbol and footprint available 3	1 Download Model

	MAX11616EEE+ Analog Devices	1	IC, ADC, 12BIT, 94.4KSPS, QSOP-16 Resolution (Bits):12 Sample Rate:94.4kSPS Input Channel Type:Differential, Single Ended Data Interface:Serial, I2C Supply Voltage Range-Analog:2.7V to 3.6V Supply Current:670µA	Small Outline Packages	MAX11616EEE+	3D model available Symbol and footprint available 3	1 Download Model
	AT28BV64B-20JU-T Microchip	1	EEPROM 200NS, PLCC, IND TEMP, GREEN, T&R 64K (8K x 8) Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection	Plastic Leaded Chip Carrier	AT28BV64B-20JU-T	3D model not available Symbol and footprint available 2	1 Download Model
	ADS8695IPW Texas Instruments	1	Analog to Digital Converters - ADC 18-Bit 500kSPS Single-Supply SAR ADC Data Acquisition System With Programmable Bipolar Input Ranges 16-TSSOP -40 to 125	Small Outline Packages	ADS8695IPW	3D model available Symbol and footprint available 3	1 Download Model
	EKMX401ELL220ML20S Chemi-Con	1	Detailed information for: EK 401. This page contains technical data sheet, documents library and links to offering related to this product.	Capacitor, Polarized Radial Diameter	EKMX401ELL220ML20S	3D model available Symbol and footprint available 3	1 Download Model
	RT0603DRE077K41L KEMET	1	DATA SHEET THIN FILM CHIP RESISTORS High precision - high stability RT series 0.01% TO 1%, TCR 5 TO 50 sizes 0201/0402/0603/0805/1206/ 1210/2010/2512	Resistor Chip	RT0603DRE077K41L	3D model available Symbol and footprint available 3	1 Download Model
	SLG55596V Renesas Electronics	1	The SLG55596 is a USB device that combines high speed USB switches with a USB host charger (dedicated charger) identification circuit. The device supports both the latest USB Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple* compliant devices as well as legacy USB D+/D- short detection using data line pull-up. The SLG55596 can also support CDP mode (FAST charging and data communication available mode if smartphone can support CDP mode). The SLG55	Small Outline No-lead	SLG55596V	3D model available Symbol and footprint available 3	1 Download Model
	7282L12PA Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L12PA	3D model available Symbol and footprint available 3	1 Download Model
	SLG55584V Renesas Electronics	1	The SLG55584 is a USB device that combines high speed USB switches with a USB host charger (dedicated charger) identification circuit. The device supports both the latest USB Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple compliant devices as well as legacy USB D+/D- short detection using data line pull-up. The SLG55584 can also support CDP mode (FAST charging and data communication available mode if smartphone can support CDP mode.) The SLG555	Small Outline No-lead	SLG55584V	3D model available Symbol and footprint available 3	1 Download Model
	SLG55593AV Renesas Electronics	1	The SLG55593A is a USB device that combines high speed USB switches with a USB host charger (dedicated charger) identification circuit. The device supports both the latest USB Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple* compliant devices as well as legacy USB D+/D- short detection using data line pull-up. The SLG55593A can also support CDP mode (FAST charging and data communication available mode if smartphone can support CDP mode.) The SLG	Small Outline No-lead	SLG55593AV	3D model available Symbol and footprint available 3	1 Download Model
	7280L12PA Renesas Electronics	1	The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7280L12PA	3D model available Symbol and footprint available 3	1 Download Model
	72T36105L6-7BB Renesas Electronics	1	The 72T36105 is a 64K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36105L6-7BB	3D model available Symbol and footprint available 3	1 Download Model

	W632GG6MB11S Winbond This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	Power Supply: VDD, VDDQ = 1.5V ± 0.075V\r\n Double Data Rate architecture: two data transfers per clock cycle\r\n Eight internal banks for concurrent operation\r\n 8 bit prefetch architecture\r\n CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n Programmable read burst ordering: interleaved or nibble sequential\r\n Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit	BGA	W632GG6MB11S	3D model available Symbol and footprint available 3	1 Download Model
	72V84L15PAG Renesas Electronics	1	The 72V84 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V84L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	SLG55583V Renesas Electronics	1	The SLG55583 is a USB device that combines high speed USB switches with a USB host charger (dedicated charger) identification circuit. The device supports both the latest USB Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple compliant devices as well as legacy USB D+/D- short detection using data line pull-up. The SLG55583 can also support CDP mode (FAST charging and data communication available mode if smartphone can support CDP mode.) The SLG555	Small Outline No-lead	SLG55583V	3D model available Symbol and footprint available 3	1 Download Model
	72T1895L6-7BB Renesas Electronics	1	The 72T1895 is a 64K x 18 / 128K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1895L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	SLG55583AV Renesas Electronics	1	The SLG55583A is a USB device that combines high speed USB switches with a USB host charger (dedicated charger) identification circuit. The device supports both the latest USB Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple compliant devices as well as legacy USB D+/D- short detection using data line pull-up. The SLG55583A can also support CDP mode (FAST charging and data communication available mode if smartphone can support CDP mode.) The SLG5	Small Outline No-lead	SLG55583AV	3D model available Symbol and footprint available 3	1 Download Model
	72T18125L5BB Renesas Electronics	1	The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18125L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72605L50J8 Renesas Electronics	1	The 72605 is a 256 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Plastic Leaded Chip Carrier	72605L50J8	3D model not available Symbol and footprint available 2	1 Download Model
	W631GG8MB11A Winbond This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	 Power Supply: VDD, VDDQ = 1.5V ± 0.075V\r\n Double Data Rate architecture: two data transfers per clock cycle\r\n Eight internal banks for concurrent operation\r\n 8 bit prefetch architecture\r\n CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n Programmable read burst ordering: interleaved or nibble sequential\r\n Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w	BGA	W631GG8MB11A	3D model available Symbol and footprint available 3	1 Download Model
	72605L20PF8 Renesas Electronics	1	The 72605 is a 256 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Quad Flat Packages	72605L20PF8	3D model available Symbol and footprint available 3	1 Download Model
	7282L15PAI Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PAI	3D model available Symbol and footprint available 3	1 Download Model
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