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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V67703S75BQGI8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67703S75BQGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S75BGG Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65703S75BGG	3D model available Symbol and footprint available 3	1 Download Model
	70T633S10BFI Renesas Electronics	1	The 70T633 is a high-speed 512K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T633S10BFI	3D model available Symbol and footprint available 3	1 Download Model
	70V7599S166BC Renesas Electronics	1	The 70V7599 is a high-speed 128K x 36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 2Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7599S166BC	3D model available Symbol and footprint available 3	1 Download Model

	709279L12PFGI Renesas Electronics	1	The 709279 is a high-speed 32K x 16 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	709279L12PFGI	3D model available Symbol and footprint available 3	1 Download Model
	70T651S12BC8 Renesas Electronics	1	The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T651S12BC8	3D model available Symbol and footprint available 3	1 Download Model
	70T3599S133BCI8 Renesas Electronics	1	The 70T3599 is a high-speed 128K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3599 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3599S133BCI8	3D model available Symbol and footprint available 3	1 Download Model
	71024S20YG Renesas Electronics	1	The 71024 5V CMOS SRAM is organized as 128K x 8. All bidirectional inputs and outputs of the 71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71024S20YG	3D model available Symbol and footprint available 3	1 Download Model
	71V547S100PFGI Renesas Electronics	1	The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V547S100PFGI	3D model available Symbol and footprint available 3	1 Download Model
	70V3389S6BF8 Renesas Electronics	1	The 70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3389 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3389S6BF8	3D model available Symbol and footprint available 3	1 Download Model
	71V424L12PHG8 Renesas Electronics	1	The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71V424L12PHG8	3D model available Symbol and footprint available 3	1 Download Model
	71T75802S200PFGI Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	Quad Flat Packages	71T75802S200PFGI	3D model available Symbol and footprint available 3	1 Download Model
	70V659S15BC8 Renesas Electronics	1	The 70V659 is a high-speed 128K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V659S15BC8	3D model available Symbol and footprint available 3	1 Download Model
	71421LA20JG Renesas Electronics	1	The 71421 is a high-speed 2K x 8 Dual-Port Static RAM with internal interrupt logic for interprocessor communications. It is designed to be used as a "SLAVE" Dual-Port RAM together with the 71321 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.	Plastic Leaded Chip Carrier	71421LA20JG	3D model not available Symbol and footprint available 2	1 Download Model
	R1Q4A4418RBG-33IB0 Renesas Electronics	1	The R1Q4A4436RBG is a 4, 194, 304-word by 36-bit and the R1Q4A4418RBG is a 8, 388, 608-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed,	BGA	R1Q4A4418RBG-33IB0	3D model available Symbol and footprint available 3	1 Download Model

	71V2556SA100BGGI Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA100BGI8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BGI8	3D model available Symbol and footprint available 3	1 Download Model
	7164S20YGI Renesas Electronics	1	The 7164 5V CMOS SRAM is organized as 8K x 8. The 7164 offers a reduced power standby mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Other	7164S20YGI	3D model available Symbol and footprint available 3	1 Download Model
	R1Q3A4436RBG-33IB0 Renesas Electronics	1	The R1Q3A4436RBG is a 4, 194, 304-word by 36-bit and the R1Q3A4418RBG is a 8, 388, 608-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed,	BGA	R1Q3A4436RBG-33IB0	3D model available Symbol and footprint available 3	1 Download Model
	71V424L10YGI8 Renesas Electronics	1	The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71V424L10YGI8	3D model available Symbol and footprint available 3	1 Download Model
	70T631S10BC8 Renesas Electronics	1	The 70T631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T631S10BC8	3D model available Symbol and footprint available 3	1 Download Model
	70V7339S133BC Renesas Electronics	1	The 70V7339 is a high-speed 512K x 18 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 8K x 18 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 8K x 18 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7339S133BC	3D model available Symbol and footprint available 3	1 Download Model
	7130LA20TFG Renesas Electronics	1	The 7130 is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535	Quad Flat Packages	7130LA20TFG	3D model available Symbol and footprint available 3	1 Download Model
	70V7599S166BC8 Renesas Electronics	1	The 70V7599 is a high-speed 128K x 36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 2Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7599S166BC8	3D model available Symbol and footprint available 3	1 Download Model
	71V67603S166BQG Renesas Electronics	1	The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin.	BGA	71V67603S166BQG	3D model available Symbol and footprint available 3	1 Download Model
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