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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V3641L15PFG8 Renesas Electronics	1	The 72V3641is a 1K x 36 Sync FIFO memory that is a 3.3V version of the 723641. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode. Communication between each port may take place with two 36-bit mailbox registers. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with sy	Quad Flat Packages	72V3641L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V293L7-5PFGI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V293L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72605L25PF Renesas Electronics	1	The 72605 is a 256 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Quad Flat Packages	72605L25PF	3D model available Symbol and footprint available 3	1 Download Model
	7207L20DB Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7207L20DB	3D model not available Symbol and footprint available 2	1 Download Model

	72615L50PF Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Quad Flat Packages	72615L50PF	3D model available Symbol and footprint available 3	1 Download Model
	7208L20JG Renesas Electronics	1	The 7208 is a 64K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7208L20JG	3D model not available Symbol and footprint available 2	1 Download Model
	72V221L15PFGI8 Renesas Electronics	1	The 72V221 is a 1K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72221 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V221L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72221L15PFGI Renesas Electronics	1	The 72221SyncFIFO™ is a 1K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72221L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	5962-8866906YA Renesas Electronics	1	The 5962-88669 (IDT 7203) is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	5962-8866906YA	3D model not available Symbol and footprint available 2	1 Download Model
	72V3632L15PFGI8 Renesas Electronics	1	The 72V3632 is a 3.3V version of the 723632. Two independent 512 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3632L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72265LA15PFGI Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	CD40105BDMSR Renesas Electronics	1	CD40105BMS is a low-power first-in-first-out (FIFO) elastic storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A 1 signifies that the position's data is filled and a 0 denotes a vacancy in that position. The control flip-flop detects the state of the preced	Ceramic Dual-In-Line Packages	CD40105BDMSR	3D model available Symbol and footprint available 3	1 Download Model
	72V3632L15PFGI Renesas Electronics	1	The 72V3632 is a 3.3V version of the 723632. Two independent 512 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3632L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V265LA10TFG Renesas Electronics	1	The 72V265 is an 16K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72265 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V265LA10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10TFG Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10TFG	3D model available Symbol and footprint available 3	1 Download Model

	723643L12PFG8 Renesas Electronics	1	The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723643L12PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V02L25JGI8 Renesas Electronics	1	The 72V02 is a 1K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V02L25JGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3611L15PFG Renesas Electronics	1	The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with	Quad Flat Packages	72V3611L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	7204L15SOGI8 Renesas Electronics	1	The 7204 is a 4K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7204L15SOGI8	3D model available Symbol and footprint available 3	1 Download Model
	7207L20JGI8 Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7207L20JGI8	3D model not available Symbol and footprint available 2	1 Download Model
	72V3690L6BB8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L6BB8	3D model available Symbol and footprint available 3	1 Download Model
	7207L15JG Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7207L15JG	3D model not available Symbol and footprint available 2	1 Download Model
	7202LA50JG Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7202LA50JG	3D model not available Symbol and footprint available 2	1 Download Model
	72275L10TFG8 Renesas Electronics	1	The 72275 is a 32K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72275L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V235L10PFG Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10PFG	3D model available Symbol and footprint available 3	1 Download Model
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