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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V293L7-5PFGI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V293L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V36110L7-5BBI Renesas Electronics	1	The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V36110L7-5BBI	3D model available Symbol and footprint available 3	1 Download Model
	7202LA12JG Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7202LA12JG	3D model not available Symbol and footprint available 2	1 Download Model
	5962-8866906YA Renesas Electronics	1	The 5962-88669 (IDT 7203) is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	5962-8866906YA	3D model not available Symbol and footprint available 2	1 Download Model

	72831L10PFG Renesas Electronics	1	The 72831 is a 2K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations s	Quad Flat Packages	72831L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72125L25SOG Renesas Electronics	1	The 72125 is a 1K x 16 dedicated, parallel-to-serial FIFOs. The ability to buffer wide word widths (x16) make this FIFO ideal for laser printers, FAX machines, local area networks (LANS), video storage and disk/tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT's unique serial expansion logic makes this possible using a minimum of pins.	Small Outline Packages	72125L25SOG	3D model available Symbol and footprint available 3	1 Download Model
	723641L15PF Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72V3680L7-5BB Renesas Electronics	1	The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3680L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V235L15TFGI8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72T36125L10BB Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L10BB	3D model available Symbol and footprint available 3	1 Download Model
	CD40105BDMSR Renesas Electronics	1	CD40105BMS is a low-power first-in-first-out (FIFO) elastic storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A 1 signifies that the position's data is filled and a 0 denotes a vacancy in that position. The control flip-flop detects the state of the preced	Ceramic Dual-In-Line Packages	CD40105BDMSR	3D model available Symbol and footprint available 3	1 Download Model
	72V3632L15PFGI Renesas Electronics	1	The 72V3632 is a 3.3V version of the 723632. Two independent 512 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3632L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V241L10PFG Renesas Electronics	1	The 72V241 is a 4K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72241 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V241L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	7283L15PAGI Renesas Electronics	1	The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7283L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	72T36105L5BBI Renesas Electronics	1	The 72T36105 is a 64K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36105L5BBI	3D model available Symbol and footprint available 3	1 Download Model

	72265LA15PFGI Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72811L10TFG8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	7284L12PAG8 Renesas Electronics	1	The 7284 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7284L12PAG8	3D model available Symbol and footprint available 3	1 Download Model
	72V841L10PFG Renesas Electronics	1	The 72V841is a 4K x 9 dual synchronous FIFO that is functionally equivalent to two 72V241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V841L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T1885L4-4BB Renesas Electronics	1	The 72T1885 is a 32K x 18 / 64K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1885L4-4BB	3D model available Symbol and footprint available 3	1 Download Model
	7205L15TPGI Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7205L15TPGI	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L6BB Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L6BB	3D model available Symbol and footprint available 3	1 Download Model
	72V251L10JG8 Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Plastic Leaded Chip Carrier	72V251L10JG8	3D model not available Symbol and footprint available 2	1 Download Model
	74HC40105D,653 Nexperia	1	74HC40105 - 4-bit x 16-word FIFO register@en-us	Small Outline Packages	74HC40105D,653	3D model available Symbol and footprint available 3	1 Download Model
	72265LA10TFG8 Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
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