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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	SN74V3640-10PEU Texas Instruments	1	FIFO 1024 x 36 Synch FIFO Memory	Quad Flat Packages	SN74V3640-10PEU	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT2226DWR Texas Instruments	1	FIFO 64 x 1 x 2 dual independent sync	Small Outline Packages	SN74ACT2226DWR	3D model available Symbol and footprint available 3	1 Download Model
	IDT72T18125L5BBI Renesas Electronics	1	IDT IDT72T18125L5BBI, FIFO Memory	BGA	IDT72T18125L5BBI	3D model available Symbol and footprint available 3	1 Download Model
	SN74V3660-6PEU Texas Instruments	1	4096 x 36 Synchronous FIFO Memory	Quad Flat Packages	SN74V3660-6PEU	3D model available Symbol and footprint available 3	1 Download Model

	SN74ACT7804-40DL Texas Instruments	1	FIFO Mem Async Dual Width Uni-Dir 512 x 18 56-Pin SSOP Tube	Small Outline Packages	SN74ACT7804-40DL	3D model available Symbol and footprint available 3	1 Download Model
	72V283L7-5PFGI8 Renesas Electronics	1	The 72V283 64K x 9/32K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V283L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V211L15PFGI Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V3660L7-5BB8 Renesas Electronics	1	The 72V3660 4K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3660L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V273L10PFG Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V273L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3680L7-5PFGI Renesas Electronics	1	The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3680L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V84L15PAG Renesas Electronics	1	The 72V84 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V84L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V201L10PFG8 Renesas Electronics	1	The 72V201 is a 256 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72201 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V201L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3660L7-5BB Renesas Electronics	1	The 72V3660 4K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3660L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5PFGI Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3690L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model
	723651L20PFGI Renesas Electronics	1	The 723651 is a 2K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723651L20PFGI	3D model available Symbol and footprint available 3	1 Download Model

	72V3640L6BB8 Renesas Electronics	1	The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3640L6BB8	3D model available Symbol and footprint available 3	1 Download Model
	72T18125L5BB Renesas Electronics	1	The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18125L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5BB Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V251L15PFGI8 Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V251L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7202LA12SOG8 Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7202LA12SOG8	3D model available Symbol and footprint available 3	1 Download Model
	72V05L15JG8 Renesas Electronics	1	The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V05L15JG8	3D model available Symbol and footprint available 3	1 Download Model
	72T36105L6-7BB Renesas Electronics	1	The 72T36105 is a 64K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36105L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72V2103L6BC Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V2103L6BC	3D model available Symbol and footprint available 3	1 Download Model
	72V245L10PFG8 Renesas Electronics	1	The 72V245 is a 4K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72245 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V245L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72211L15PFGI8 Renesas Electronics	1	The 72211SyncFIFO™ is a 512 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72211L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
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