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71V67602S133PFGI
Renesas Electronics
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1 | The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V67602S133PFGI |
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71V3556S100PFGI
Renesas Electronics
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1 | The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers. | Quad Flat Packages | 71V3556S100PFGI |
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70T659S10BCI8
Renesas Electronics
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1 | The 70T659 is a high-speed 128K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. | BGA | 70T659S10BCI8 |
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7130SA100C
Renesas Electronics
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1 | The 7130 is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 | Ceramic Dual-In-Line Packages | 7130SA100C |
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71V424L15YG
Renesas Electronics
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1 | The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. | Other | 71V424L15YG |
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71T75602S150BGG8
Renesas Electronics
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1 | The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers. | BGA | 71T75602S150BGG8 |
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71V67602S166BGG8
Renesas Electronics
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1 | The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V67602S166BGG8 |
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R1LP5256ESP-5SR#B0
Renesas Electronics
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1 | Support is limited to customers who have already adopted these products.Renesas is the worldwide #1 Low Power SRAM supplier with a full lineup and well balanced long term support. High density and high performance RAMs using Renesas's original technology, for example the Advanced LPSRAM new memory cell concept are offered. | Small Outline Packages | R1LP5256ESP-5SR#B0 |
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71V3577S75BQG8
Renesas Electronics
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1 | The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V3577S75BQG8 |
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71V65803S100PFG8
Renesas Electronics
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1 | The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V65803S100PFG8 |
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71V416L12YGI8
Renesas Electronics
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1 | The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. | Other | 71V416L12YGI8 |
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71V67903S80BQ8
Renesas Electronics
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1 | The 71V67903 3.3V CMOS SRAM is organized as 512K x 18. The 71V67903 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V67903S80BQ8 |
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6116LA150DB
Renesas Electronics
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1 | The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available. | Dual-In-Line Packages | 6116LA150DB |
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71V124SA12TYG8
Renesas Electronics
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1 | The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. | Other | 71V124SA12TYG8 |
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70V3579S4BF
Renesas Electronics
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1 | The 70V3579 is a high-speed 32K × 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3579 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | BGA | 70V3579S4BF |
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6116LA20SOGI
Renesas Electronics
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1 | The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available. | Small Outline Packages | 6116LA20SOGI |
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71V67903S85BQI8
Renesas Electronics
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1 | The 71V67903 3.3V CMOS SRAM is organized as 512K x 18. The 71V67903 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V67903S85BQI8 |
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71016S12YG8
Renesas Electronics
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1 | The 71016 5V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71016 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. | Other | 71016S12YG8 |
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71V424S12YG8
Renesas Electronics
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1 | The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. | Other | 71V424S12YG8 |
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70V9289L7PFG8
Renesas Electronics
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1 | The 70V9289 is a high-speed 64K x 16-bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. | Quad Flat Packages | 70V9289L7PFG8 |
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71V3557S80BG
Renesas Electronics
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1 | The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). | BGA | 71V3557S80BG |
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7133SA35GB
Renesas Electronics
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1 | The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available. | Other | 7133SA35GB |
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70T3319S166BC8
Renesas Electronics
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1 | The 70T3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. | BGA | 70T3319S166BC8 |
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71V65603S100PFG8
Renesas Electronics
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1 | The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V65603S100PFG8 |
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5962-8687502XA
Renesas Electronics
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1 | The 5962-86875 (IDT 7130/40) is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with | Ceramic Dual-In-Line Packages | 5962-8687502XA |
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