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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	70V7519S133BCI8 Renesas Electronics	1	The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7519S133BCI8	3D model available Symbol and footprint available 3	1 Download Model
	70T651S12BCI8 Renesas Electronics	1	The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T651S12BCI8	3D model available Symbol and footprint available 3	1 Download Model
	71V416L10BE Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L10BE	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S133BG Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S133BG	3D model available Symbol and footprint available 3	1 Download Model

	71V3556SA100BGGI8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	71T75802S200BGG8 Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	BGA	71T75802S200BGG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S75BQG Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65703S75BQG	3D model available Symbol and footprint available 3	1 Download Model
	71T75902S75PFGI8 Renesas Electronics	1	The 71T75902 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround.	Quad Flat Packages	71T75902S75PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V7519S133BF Renesas Electronics	1	The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7519S133BF	3D model available Symbol and footprint available 3	1 Download Model
	70V658S10BC8 Renesas Electronics	1	The 70V658 is a high-speed 64K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V658S10BC8	3D model available Symbol and footprint available 3	1 Download Model
	71V25761S183PFG Renesas Electronics	1	The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V25761S183PFG	3D model available Symbol and footprint available 3	1 Download Model
	70T3599S133BFGI8 Renesas Electronics	1	The 70T3599 is a high-speed 128K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3599 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3599S133BFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V658S15BF Renesas Electronics	1	The 70V658 is a high-speed 64K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V658S15BF	3D model available Symbol and footprint available 3	1 Download Model
	70V38L20PFGI Renesas Electronics	1	The 70V38 is a high-speed 64K x 18 Dual-Port Static RAM designed to be used as a stand-alone 576K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more word systems. This MASTER/SLAVE approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V38L20PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3559S80BGI8 Renesas Electronics	1	The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	BGA	71V3559S80BGI8	3D model available Symbol and footprint available 3	1 Download Model

	7025L20G Renesas Electronics	1	The 7025 is a high-speed 8K x 16 Dual-Port Static RAM designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7025L20G	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA150BGG8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA150BGG8	3D model available Symbol and footprint available 3	1 Download Model
	70T3319S133BFGI8 Renesas Electronics	1	The 70T3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3319S133BFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V658S10DRG Renesas Electronics	1	The 70V658 is a high-speed 64K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	Quad Flat Packages	70V658S10DRG	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA166BGI Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA166BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V547S80PFGI8 Renesas Electronics	1	The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V547S80PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V28L20PFG Renesas Electronics	1	The 70V28 is a high-speed 64K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or wider memory system applications resulting in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V28L20PFG	3D model available Symbol and footprint available 3	1 Download Model
	71124S20YG8 Renesas Electronics	1	The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71124S20YG8	3D model available Symbol and footprint available 3	1 Download Model
	71V67602S150PFGI8 Renesas Electronics	1	The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67602S150PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA133BQG Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA133BQG	3D model available Symbol and footprint available 3	1 Download Model
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