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| Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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1S4A_0303S1.5UP
Gaptec
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1 | 1W - Single Output - Fixed Input - Isolated & Unregulated SIP PACKAGE | Other | 1S4A_0303S1.5UP |
3
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71V65603S150BQ
Renesas Electronics
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1 | The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65603S150BQ |
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C0603S152K5RACAUTO
Yageo Group
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1 | SMD, MLCC, FE-CAP, Floating Electrode, Automotive Grade | Other | C0603S152K5RACAUTO |
3
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ASPI-0403S-152M-T
ABRACON
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1 | FIXED IND 1.5MH 120MA 4.2 OHM | Other | ASPI-0403S-152M-T |
2
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71V65603S150BQGI8
Renesas Electronics
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1 | The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65603S150BQGI8 |
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SDF03S1515
Summit Electronics
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1 | 3W 15V DC/DC ConverterInput Voltage [VDC] 15 , Output Voltage (VDC) 15 , Output Current (mA) Max , 200 , Capacitiv Load (uF) Max.220 ,SIP7 , -40 ~ +85°C | Other | SDF03S1515 |
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1T8A_0303S1.5U
Gaptec
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1 | 1W - Single Output DC-DC Converter - Fixed Input - Isolated & Unregulated | Other | 1T8A_0303S1.5U |
3
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1S4A_1203S1.5UP
Gaptec
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1 | 1W - Single Output - Fixed Input - Isolated & Unregulated SIP PACKAGE | Other | 1S4A_1203S1.5UP |
3
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C0603S153K5RACAUTO
Yageo Group
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1 | SMD, MLCC, FE-CAP, Floating Electrode, Automotive Grade | Other | C0603S153K5RACAUTO |
3
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3S7A_0503S1.5UP
Gaptec
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1 | Isolated Module DC DC Converter 1 Output 3.3V 909mA 4.5V - 5.5V Input -40°C ~ 105°C 7SIP | Other | 3S7A_0503S1.5UP |
3
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15DMW_4803S1.5
Gaptec
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1 | 15W - Single Output - Wide Input - Isolated & Regulated 1? x 1? DC-DC Converter | Other | 15DMW_4803S1.5 |
3
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20DMW_1203S1.5
Gaptec
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1 | 20W - Single Output - Ultra Wide Input - Isolated & Regulated DC-DC Converter | Other | 20DMW_1203S1.5 |
3
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71V67603S150BGGI
Renesas Electronics
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1 | The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin. | BGA | 71V67603S150BGGI |
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71V65603S150BGG8
Renesas Electronics
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1 | The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65603S150BGG8 |
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71V65803S150BG
Renesas Electronics
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1 | The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65803S150BG |
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71V65803S150BGI
Renesas Electronics
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1 | The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65803S150BGI |
3
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3S8EW_2403S1.5RP
Gaptec
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1 | 3W - Single Output - Wide Input - Isolated & Regulated DC-DC Converter | Other | 3S8EW_2403S1.5RP |
3
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0.1MD4A_0503S1.5U
Gaptec
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1 | 0.1W - Single Output DC-DC Converter - Fixed Input - Isolated & Unregulated | Other | 0.1MD4A_0503S1.5U |
3
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ASPI-0403S-151M-T
ABRACON
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1 | FIXED IND 150UH 260MA 590 MOHM | Other | ASPI-0403S-151M-T |
2
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71V65603S150BQ8
Renesas Electronics
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1 | The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65603S150BQ8 |
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1S4A_2403S1.5U
Gaptec
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1 | 1W - Single Output - Fixed Input - Isolated & Unregulated SIP PACKAGE | Other | 1S4A_2403S1.5U |
3
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0.1S4A_0503S1.5U
Gaptec
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1 | 0.1W - Single Output - Fixed Input - Isolated & Unregulated MINIATURE SIP PACKAGE, DC-DC Converter | Other | 0.1S4A_0503S1.5U |
3
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71V65803S150BQ
Renesas Electronics
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1 | The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65803S150BQ |
3
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71V67803S150PFGI
Renesas Electronics
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1 | The 71V67803 3.3V CMOS SRAM is organized as 512K x 18. The 71V67803 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V67803S150PFGI |
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71V67603S150PFGI8
Renesas Electronics
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1 | The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin. | Quad Flat Packages | 71V67603S150PFGI8 |
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