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	2308A-4DCG8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-4DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-2DCGI Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-2DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2308A-2DCG8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-2DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1HDCGI Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HDCGI	3D model available Symbol and footprint available 3	1 Download Model

	2308A-1HDCG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HDCG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-4DCGI Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-4DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1DCG8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1HPGG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HPGG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-4DCG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-4DCG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1HPGGI Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HPGGI	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1HPGG8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HPGG8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1DCGI Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1HDCG8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HDCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-2DCGI8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-2DCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-3DCGI Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-3DCGI	3D model available Symbol and footprint available 3	1 Download Model

	2308A-1HPGGI8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HPGGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-2HDCG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-2HDCG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1DCGI8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1DCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1DCG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1DCG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-4DCGI8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-4DCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-3DCG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-3DCG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-1HDCGI8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-2DCG Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-2DCG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-5HPGG8 Renesas Electronics	1	Clock Generators & Support Products 3.3V PLL ZERO DELAY CLOCK MULTIPLIER	Small Outline Packages	2308A-5HPGG8	3D model available Symbol and footprint available 3	1 Download Model
	2308A-5HPGG Renesas Electronics	1	Clock Generators & Support Products 3.3V PLL ZERO DELAY CLOCK MULTIPLIER	Small Outline Packages	2308A-5HPGG	3D model available Symbol and footprint available 3	1 Download Model
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