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2308B-1DCGI
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1DCGI |
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2308B-1HDCGI8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HDCGI8 |
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2308B-1DCG8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1DCG8 |
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2308B-2DCGI
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-2DCGI |
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2308B-1DCG
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1DCG |
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2308B-1DCGI8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1DCGI8 |
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2308B-4DCG
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-4DCG |
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2308B-1HPGGI
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HPGGI |
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2308B-1HPGG8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HPGG8 |
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2308B-2DCG8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-2DCG8 |
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2308B-2DCG
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-2DCG |
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2308B-1HPGG
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HPGG |
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2308B-1HDCGI
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HDCGI |
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2308B-2DCGI8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-2DCGI8 |
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2308B-1HPGGI8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HPGGI8 |
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2308B-4DCG8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-4DCG8 |
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2308B-1HDCG
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HDCG |
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2308B-1HDCG8
Renesas Electronics
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1 | The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the | Small Outline Packages | 2308B-1HDCG8 |
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SI2308BDS-T1-GE3
Vishay
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1 | SI2308BDS-T1-GE3, N-channel MOSFET Transistor 1.9 A 60 V, 3-Pin SOT-23 | SOT23 (3-Pin) | SI2308BDS-T1-GE3 |
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PAM2308BYMAA
Diodes Incorporated
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1 | Switching Voltage Regulators DUAL HI-EFF PWM SD DC/DC CNVTR | Small Outline No-lead | PAM2308BYMAA |
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TD62308BP1G(O,J)
Toshiba
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1 | Toshiba TD62308BP1G(O,J) Quad NPN+PNP Darlington Transistor Array, 1.5 A 80 V, 16-Pin PDIP | Dual-In-Line Packages | TD62308BP1G(O,J) |
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SI2308BDS-T1-E3
Vishay
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1 | Vishay SI2308BDS-T1-E3 N-channel MOSFET Module, 2.3 A, 60 V, 3-Pin TO-236 | SOT23 (3-Pin) | SI2308BDS-T1-E3 |
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IDT2308B-4DC8
Renesas Electronics
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1 | Renesas Electronics | Small Outline Packages | IDT2308B-4DC8 |
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IDT2308B-4DC
Renesas Electronics
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1 | Renesas Electronics | Small Outline Packages | IDT2308B-4DC |
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IDT2308B-1HPG8
Renesas Electronics
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1 | Multiplier, Zero Delay Buffer IC 133.3MHz 1 16-SOIC (0.154", 3.90mm Width) | Small Outline Packages | IDT2308B-1HPG8 |
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