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IPD70N10S3L-12
Infineon
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1 | Infineon IPD70N10S3L-12 N-channel MOSFET Transistor, 70 A, 100 V, 3-Pin TO-252 | Other | IPD70N10S3L-12 |
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FX23L-120P-0.5SV10
Hirose
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1 | CONN HDR | Other | FX23L-120P-0.5SV10 |
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IPB70N10S3L-12
Infineon
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1 | MOSFET N-Ch 100V 70A D2PAK-2 OptiMOS-T | Other | IPB70N10S3L-12 |
3
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7203L12TPG
Renesas Electronics
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1 | The 7203 is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Dual-In-Line Packages | 7203L12TPG |
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HFJT1-E1G20C3-L12RL
Halo Electronics
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1 | Modular Connectors / Ethernet Connectors 1G EXTTEMP 1x1 TabUp RJ45 w/MAG G/Y LED | Other | HFJT1-E1G20C3-L12RL |
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AS4C256M16D3L-12BIN
Alliance Memory
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1 | DRAM 4G 1.35V 1600Mhz 256M x 16 DDR3 | BGA | AS4C256M16D3L-12BIN |
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IDT7203L12TPG
Renesas Electronics
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1 | IDT IDT7203L12TPG, FIFO Memory, Dual 18kbit, 2K x 9 bit, Bi-Directional 12ns, 4.5 → 5.5 V, 28-Pin PDIP | Dual-In-Line Packages | IDT7203L12TPG |
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723643L12PF
Renesas Electronics
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1 | The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. | Quad Flat Packages | 723643L12PF |
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HFJT1-E10G06C3-L12RL
Halo Electronics
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1 | Modular Connectors / Ethernet Connectors FastJack 10G TABUP RJ45 W/ MAG G/Y LED | Other | HFJT1-E10G06C3-L12RL |
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SPU03L-12
Mean Well
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1 | Isolated DC/DC Converters | Other | SPU03L-12 |
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FX23L-120P-0.5SV8
Hirose
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1 | 120p mezzanine header | Other | FX23L-120P-0.5SV8 |
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FX23L-120S-0.5SV
Hirose
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1 | Board to Board & Mezzanine Connectors | Other | FX23L-120S-0.5SV |
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723623L12PFG
Renesas Electronics
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1 | The 723623 is a 256 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. | Quad Flat Packages | 723623L12PFG |
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MLK0603L12NJT000
TDK
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1 | SMD / SMT Inductors (Coils), L=12nH, L x W x T : | Inductors Chip | MLK0603L12NJT000 |
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723633L12PF8
Renesas Electronics
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1 | The 723633 is a 512 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. | Quad Flat Packages | 723633L12PF8 |
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723663L12PF
Renesas Electronics
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1 | The 723663 is a 4K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. This device can operate in the IDT Standard mode | Quad Flat Packages | 723663L12PF |
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7283L12PA8
Renesas Electronics
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1 | The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7283L12PA8 |
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IDT7203L12JG
Renesas Electronics
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1 | IDT IDT7203L12JG, FIFO Memory, Dual 18kbit, 2K x 9 bit, Bi-Directional 12ns, 4.5 → 5.5 V, 32-Pin PLCC | Plastic Leaded Chip Carrier | IDT7203L12JG |
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AS4C1G8MD3L-12BCN
Alliance Memory
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1 | DRAM DDR3, 8GB. 1.35V 800MHz,1G x 8 | BGA | AS4C1G8MD3L-12BCN |
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AS4C128M16D3L-12BANTR
Alliance Memory
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1 | IC DRAM 2GBIT PARALLEL 96BGA | BGA | AS4C128M16D3L-12BANTR |
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445I23L12M00000
CTS
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1 | Crystals 12MHz +/-20ppm 12pF -40C +85C | Other | 445I23L12M00000 |
3
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7203L12JG8
Renesas Electronics
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1 | The 7203 is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Plastic Leaded Chip Carrier | 7203L12JG8 |
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723643L12PFG
Renesas Electronics
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1 | The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. | Quad Flat Packages | 723643L12PFG |
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7283L12PAG8
Renesas Electronics
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1 | The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7283L12PAG8 |
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723623L12PFG8
Renesas Electronics
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1 | The 723623 is a 256 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. | Quad Flat Packages | 723623L12PFG8 |
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