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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72261 Renesas Electronics Corporation	1	FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64		72261	3D model not available Symbol and footprint not available 0	0 Build or Request
	72261 Integrated Device Technology Inc	1	FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64		72261	3D model not available Symbol and footprint not available 0	0 Build or Request
	72261LA15TFGI8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA10PFG8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA10PFG8	3D model available Symbol and footprint available 3	1 Download Model

	72261LA15TFGI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFGI	3D model available Symbol and footprint available 3	1 Download Model
	72261LA10PFG Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15PF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20PFI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20PFI	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15TFI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20TFI8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15TF Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TF	3D model available Symbol and footprint available 3	1 Download Model
	72261LA10PF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20PF Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20PF	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20PFI8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20TF Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20TF	3D model available Symbol and footprint available 3	1 Download Model

	72261LA15TFI8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15PF Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15PF	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15PFI8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA10PF Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA10PF	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20TF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20TF8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20PF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20PF8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15TF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA10TF Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA10TF	3D model available Symbol and footprint available 3	1 Download Model
	72261LA20TFI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA20TFI	3D model available Symbol and footprint available 3	1 Download Model
	72261LA10TF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA10TF8	3D model available Symbol and footprint available 3	1 Download Model
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