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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	723643L12PFG Renesas Electronics	1	The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723643L12PFG	3D model available Symbol and footprint available 3	1 Download Model
	723643L12PFG8 Renesas Electronics	1	The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723643L12PFG8	3D model available Symbol and footprint available 3	1 Download Model
	723641L15PF Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L15PF	3D model available Symbol and footprint available 3	1 Download Model
	723641L15PFG8 Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L15PFG8	3D model available Symbol and footprint available 3	1 Download Model

	723643L12PF Renesas Electronics	1	The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723643L12PF	3D model available Symbol and footprint available 3	1 Download Model
	723646L12PF Renesas Electronics	1	The 723646 is a 1K x 36 x 2 Triple Bus sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. FIFO data can be read out and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. The clocks for each port are independent of one another and can be asynchronous or coincident. Communication between each port may bypass the FIFOs via two mailbox registers. These devices can operate in the IDT Standard mode or First Wo	Quad Flat Packages	723646L12PF	3D model available Symbol and footprint available 3	1 Download Model
	723642L15PF Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L15PF	3D model available Symbol and footprint available 3	1 Download Model
	723641L15PFG Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	723643L15PF Renesas Electronics	1	The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723643L15PF	3D model available Symbol and footprint available 3	1 Download Model
	723644L12PF8 Renesas Electronics	1	The 723644 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723644L12PF8	3D model available Symbol and footprint available 3	1 Download Model
	723641L20PFI Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L20PFI	3D model available Symbol and footprint available 3	1 Download Model
	723644L15PF8 Renesas Electronics	1	The 723644 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723644L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	723646L15PF Renesas Electronics	1	The 723646 is a 1K x 36 x 2 Triple Bus sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. FIFO data can be read out and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. The clocks for each port are independent of one another and can be asynchronous or coincident. Communication between each port may bypass the FIFOs via two mailbox registers. These devices can operate in the IDT Standard mode or First Wo	Quad Flat Packages	723646L15PF	3D model available Symbol and footprint available 3	1 Download Model
	723642L15PF8 Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	723641L20PFI8 Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L20PFI8	3D model available Symbol and footprint available 3	1 Download Model

	723644L12PF Renesas Electronics	1	The 723644 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723644L12PF	3D model available Symbol and footprint available 3	1 Download Model
	723642L12PF8 Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L12PF8	3D model available Symbol and footprint available 3	1 Download Model
	723644L15PF Renesas Electronics	1	The 723644 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723644L15PF	3D model available Symbol and footprint available 3	1 Download Model
	723641L15PF8 Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	723646L15PF8 Renesas Electronics	1	The 723646 is a 1K x 36 x 2 Triple Bus sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. FIFO data can be read out and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. The clocks for each port are independent of one another and can be asynchronous or coincident. Communication between each port may bypass the FIFOs via two mailbox registers. These devices can operate in the IDT Standard mode or First Wo	Quad Flat Packages	723646L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	723643L12PF8 Renesas Electronics	1	The 723643 is a 1K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723643L12PF8	3D model available Symbol and footprint available 3	1 Download Model
	723642L15PFG Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	723641L20PF8 Renesas Electronics	1	The 723641 is a 1K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723641L20PF8	3D model available Symbol and footprint available 3	1 Download Model
	723642L15PFG8 Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	723646L12PF8 Renesas Electronics	1	The 723646 is a 1K x 36 x 2 Triple Bus sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. FIFO data can be read out and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. The clocks for each port are independent of one another and can be asynchronous or coincident. Communication between each port may bypass the FIFOs via two mailbox registers. These devices can operate in the IDT Standard mode or First Wo	Quad Flat Packages	723646L12PF8	3D model available Symbol and footprint available 3	1 Download Model
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