72V29 Footprint, Symbol and 3D Model search results

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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V295L10PFG8 Renesas Electronics	1	The 72V295 is an 128K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72V295L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V293L7-5PFGI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V293L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V293L6PFG Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V293L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V295L10PFG Renesas Electronics	1	The 72V295 is an 128K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72V295L10PFG	3D model available Symbol and footprint available 3	1 Download Model

	72V293L7-5BCI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V293L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72V291L10TFG8 Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V291L10TFG Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V293L7-5BC Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V293L7-5BC	3D model available Symbol and footprint available 3	1 Download Model
	72V293L6BC Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V293L6BC	3D model available Symbol and footprint available 3	1 Download Model
	72V291L10TF8 Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V291L15TF8 Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V291L15TFI8 Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72V291L20TF8 Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L20TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V291L15TFI Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72V291L20TF Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L20TF	3D model available Symbol and footprint available 3	1 Download Model

	72V291L10TF Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L10TF	3D model available Symbol and footprint available 3	1 Download Model
	72V291L15TF Renesas Electronics	1	The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co	Quad Flat Packages	72V291L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72V291L20TFG8 Renesas Electronics Corporation	1	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64		72V291L20TFG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V293L7-5BCGI8 Renesas Electronics Corporation	1	FIFO, 64KX18, 5ns, Synchronous, CMOS, PBGA100		72V293L7-5BCGI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V293L6BCG Integrated Device Technology Inc	1	FIFO, 64KX18, 4ns, Synchronous, CMOS, PBGA100		72V293L6BCG	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V293L10PFI Integrated Device Technology Inc	1	FIFO, 64KX18, 6.5ns, Synchronous, CMOS, PQFP80		72V293L10PFI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V291L15PFI Integrated Device Technology Inc	1	FIFO, 128KX9, 10ns, Synchronous, CMOS, PQFP64		72V291L15PFI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V291L15TFI9 Integrated Device Technology Inc	1	FIFO, 128KX9, 10ns, Synchronous, CMOS, PQFP64		72V291L15TFI9	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V295L20PFG Renesas Electronics Corporation	1	FIFO, 128KX18, 12ns, Synchronous, CMOS, PQFP64		72V295L20PFG	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V293L7-5PFG Integrated Device Technology Inc	1	FIFO, 64KX18, 5ns, Synchronous, CMOS, PQFP80		72V293L7-5PFG	3D model not available Symbol and footprint not available 0	0 Build or Request
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