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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V81L15PAG Renesas Electronics	1	The 72V81 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V81L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V81L15PAG8 Renesas Electronics	1	The 72V81 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V81L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	72V815L10PFG Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V811L10TFG Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L10TFG	3D model available Symbol and footprint available 3	1 Download Model

	72V811L10TFG8 Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V815L15PF8 Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V815L10PF8 Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V815L10PF Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L10PF	3D model available Symbol and footprint available 3	1 Download Model
	72V815L20PF Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L20PF	3D model available Symbol and footprint available 3	1 Download Model
	72V811L10TF Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L10TF	3D model available Symbol and footprint available 3	1 Download Model
	72V811L10TF8 Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V815L15PFI8 Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72V811L15TFI Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72V811L15TFI8 Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72V815L15PF Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L15PF	3D model available Symbol and footprint available 3	1 Download Model

	72V811L15TF8 Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V811L20TF8 Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L20TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V811L15TF Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72V811L20TF Renesas Electronics	1	The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V811L20TF	3D model available Symbol and footprint available 3	1 Download Model
	72V815L15PFI Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L15PFI	3D model available Symbol and footprint available 3	1 Download Model
	72V815L20PF8 Renesas Electronics	1	The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V815L20PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V81L20PAGI Integrated Device Technology Inc	1	FIFO, 512X9, 20ns, Asynchronous, CMOS, PDSO56		72V81L20PAGI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V81L20PAGI Renesas Electronics Corporation	1	Bi-Directional FIFO		72V81L20PAGI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V81L15PA8 Integrated Device Technology Inc	1	FIFO, 512X9, 15ns, Asynchronous, CMOS, PDSO56		72V81L15PA8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V81L20PA8 Integrated Device Technology Inc	1	FIFO, 512X9, 20ns, Asynchronous, CMOS, PDSO56		72V81L20PA8	3D model not available Symbol and footprint not available 0	0 Build or Request
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