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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V82L15PAG Renesas Electronics	1	The 72V82 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V82L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V82L20PAGI8 Renesas Electronics	1	FIFO 1K x 9 DualAsync FIFO 3.3V 15ns	Small Outline Packages	72V82L20PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V82L15PAG8 Renesas Electronics	1	FIFO 1K x 9 DualAsync FIFO 3.3V 15ns	Small Outline Packages	72V82L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	72V825L15PFI8 Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L15PFI8	3D model available Symbol and footprint available 3	1 Download Model

	72V821L20TF8 Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L20TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V821L15TFI8 Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72V821L15TF8 Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V821L10TF8 Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V825L20PF8 Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L20PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V825L15PFI Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L15PFI	3D model available Symbol and footprint available 3	1 Download Model
	72V825L15PF Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72V821L20TF Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L20TF	3D model available Symbol and footprint available 3	1 Download Model
	72V825L15PF8 Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V821L15TF Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72V825L10PF8 Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L10PF8	3D model available Symbol and footprint available 3	1 Download Model

	72V821L15TFI Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72V825L20PF Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L20PF	3D model available Symbol and footprint available 3	1 Download Model
	72V825L10PF Renesas Electronics	1	The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V825L10PF	3D model available Symbol and footprint available 3	1 Download Model
	72V821L10TF Renesas Electronics	1	The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V821L10TF	3D model available Symbol and footprint available 3	1 Download Model
	IDT72V82L15PAG Renesas Electronics	1	IDT IDT72V82L15PAG, FIFO Memory, Dual 9kbit, 1K x 9 bit, Bi-Directional 15ns, 3 → 3.6 V, 56-Pin TSSOP	Small Outline Packages	IDT72V82L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V82L20PA8 Integrated Device Technology Inc	1	FIFO, 1KX9, 20ns, Asynchronous, CMOS, PDSO56		72V82L20PA8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V82L15PAGI8 Renesas Electronics Corporation	1	FIFO		72V82L15PAGI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V82L20PAG8 Integrated Device Technology Inc	1	FIFO, 1KX9, 20ns, Asynchronous, CMOS, PDSO56		72V82L20PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V82L20PAGI8 Integrated Device Technology Inc	1	FIFO, 1KX9, 20ns, Asynchronous, CMOS, PDSO56		72V82L20PAGI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V82L15PAG8 Integrated Device Technology Inc	1	FIFO, 1KX9, 15ns, Asynchronous, CMOS, PDSO56, GREEN, TSSOP-56		72V82L15PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
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