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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V85L15PAG8 Renesas Electronics	1	The 72V85 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V85L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	72V85L15PAG Renesas Electronics	1	The 72V85 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V85L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10PFG8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10TFG Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10TFG	3D model available Symbol and footprint available 3	1 Download Model

	72V851L10TFG8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10PFG Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V85L15PA Renesas Electronics	1	The 72V85 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V85L15PA	3D model available Symbol and footprint available 3	1 Download Model
	72V85L20PA Renesas Electronics	1	The 72V85 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V85L20PA	3D model available Symbol and footprint available 3	1 Download Model
	72V85L15PA8 Renesas Electronics	1	The 72V85 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V85L15PA8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10TF8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L20TF Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L20TF	3D model available Symbol and footprint available 3	1 Download Model
	72V851L15TF Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72V851L20TF8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L20TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L15TFI8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L15TF8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L15TF8	3D model available Symbol and footprint available 3	1 Download Model

	72V851L10TF Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10TF	3D model available Symbol and footprint available 3	1 Download Model
	72V851L15TFI Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72V85L20PAGI Renesas Electronics Corporation	1	Bi-Directional FIFO		72V85L20PAGI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L15PAG Integrated Device Technology Inc	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		72V85L15PAG	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L20PAGI8 Renesas Electronics Corporation	1	Bi-Directional FIFO		72V85L20PAGI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L20PAG8 Integrated Device Technology Inc	1	FIFO, 8KX9, 20ns, Asynchronous, CMOS, PDSO56		72V85L20PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L15PA Integrated Device Technology Inc	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		72V85L15PA	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L15PAG8 Integrated Device Technology Inc	1	Bi-Directional FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		72V85L15PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L20PAG Renesas Electronics Corporation	1	Bi-Directional FIFO, 8KX9, 20ns, Asynchronous, CMOS, PDSO56		72V85L20PAG	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V85L15PAGI8 Integrated Device Technology Inc	1	FIFO		72V85L15PAGI8	3D model not available Symbol and footprint not available 0	0 Build or Request
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