B10P- Footprint, Symbol and 3D Model search results

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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	B10P-VH-FB-B(LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	CONN HEADER VERT 10POS 3.96MM	Other	B10P-VH-FB-B(LF)(SN)	3D model available Symbol and footprint available 3	1 Download Model
	B10P-SHF-1AA(LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	JST HVQ Series, 2.5mm Pitch 10 Way 1 Row Straight PCB Header, Solder Termination, 3A	Header, Vertical	B10P-SHF-1AA(LF)(SN)	3D model available Symbol and footprint available 3	1 Download Model
	B10P-VH JST (JAPAN SOLDERLESS TERMINALS)	1	Connector Header Through Hole 10 position 0.156" (3.96mm)	Other	B10P-VH	3D model not available Symbol and footprint available 2	1 Download Model
	B10P-VH(LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	Connector Header Through Hole 10 position 0.156" (3.96mm)	Other	B10P-VH(LF)(SN)	3D model not available Symbol and footprint available 2	1 Download Model

	B10P-VH (LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	Conn Wire to Board HDR 10 POS 3.96mm Solder ST Top Entry Thru-Hole Box	Header, Shrouded - Straight PTH Box	B10P-VH (LF)(SN)	3D model available Symbol and footprint available 3	1 Download Model
	B10P-SHF-1AA_(LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	Connector Header Through Hole 10 position 0.098" (2.50mm),-25°C ~ 85°C,250V,3A	Other	B10P-SHF-1AA_(LF)(SN)	3D model available Symbol and footprint available 3	1 Download Model
	B10PS-VH(LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	Pin Header, Wire-to-Board, 3.96 mm, 1 Rows, 10 Contacts, Through Hole Right Angle, VH	Other	B10PS-VH(LF)(SN)	3D model not available Symbol and footprint available 2	1 Download Model
	CIB10P100NC SAMSUNG	1	chip inductor	Inductors Chip	CIB10P100NC	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10PFG Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72225LB10PFG8 Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72245LB10PF Renesas Electronics	1	The 72245 is a 4K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72245LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72845LB10PF Renesas Electronics	1	The 72845 is a 4K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72845LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72225LB10PF Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10PF Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72815LB10PF8 Renesas Electronics	1	The 72815 is a 512 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72215 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72815LB10PF8	3D model available Symbol and footprint available 3	1 Download Model

	IX80G-B-10P Hirose	1	I/O Connectors IX Vertical Type B	Other	IX80G-B-10P	3D model available Symbol and footprint available 3	1 Download Model
	BZD27B10P-M3-08 Vishay	1	DIODE ZENER 10V 800MW DO219AB	Small Outline Diode Flat Lead	BZD27B10P-M3-08	3D model available Symbol and footprint available 3	1 Download Model
	AT24C64B-10PU-2.7 Microchip	1	Atmel AT24C64B-10PU-2.7 EEPROM Memory, 64kbit, 0.6μs, 1.8 → 5.5 V 8-Pin PDIP	Dual-In-Line Packages	AT24C64B-10PU-2.7	3D model available Symbol and footprint available 3	1 Download Model
	IX61G2-B-10P Hirose	1	Modular Connectors / Ethernet Connectors No of contacts 10	Other	IX61G2-B-10P	3D model available Symbol and footprint available 3	1 Download Model
	B10PS-VH (LF)(SN) JST (JAPAN SOLDERLESS TERMINALS)	1	JST VH, 10 Way, 1 Row, Right Angle PCB Header	Other	B10PS-VH (LF)(SN)	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10PF8 Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72805LB10PFG Renesas Electronics	1	The 72805 is a 256 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72205 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for si	Quad Flat Packages	72805LB10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72245LB10PF8 Renesas Electronics	1	The 72245 is a 4K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72245LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10PFG8 Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72805LB10PF Renesas Electronics	1	The 72805 is a 256 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72205 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for si	Quad Flat Packages	72805LB10PF	3D model available Symbol and footprint available 3	1 Download Model
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