W631GG6MB-11 Model Download Search Results

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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	W631GG6MB-11 Winbond	1	DRAM Chip DDR3 SDRAM 1Gbit 64Mx16 1.5V 96-Pin VFBGA	BGA	W631GG6MB-11	3D model available Symbol and footprint available 3	1 Download Model
	W631GG6MB11K Winbond	1	1Gb DDR3 SDRAM 1866MHz VFBGA96	BGA	W631GG6MB11K	3D model available Symbol and footprint available 3	1 Download Model
	W631GG6MB11W Winbond	1	 Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR) Precharged Power Down and Active Power Down Data masks (DM) for write data Programmable CAS Write Latency (CWL) per operating frequency Write Latency WL = AL + CWL Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence System level timing calibration support via write leveling and MPR read pattern ZQ Calibration for output driver and ODT using external reference r	BGA	W631GG6MB11W	3D model available Symbol and footprint available 3	1 Download Model
	W631GG6MB11A Winbond	1	Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit	BGA	W631GG6MB11A	3D model available Symbol and footprint available 3	1 Download Model

	W631GG6MB11S Winbond	1	 Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w	BGA	W631GG6MB11S	3D model available Symbol and footprint available 3	1 Download Model
	W631GG6MB11J Winbond Electronics Corp	1	DDR3 DRAM, 64MX16, CMOS, PBGA96		W631GG6MB11J	3D model not available Symbol and footprint not available 0	0 Build or Request

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