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Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action |
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Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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W638GU6QB-09
Winbond
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1 | Data masks (DM) for write data\r\n⚫ Programmable CAS Write Latency (CWL) per operating frequency\r\n⚫ Write Latency WL = AL + CWL\r\n⚫ Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence\r\n⚫ System level timing calibration support via write leveling and MPR read pattern\r\n⚫ ZQ Calibration for output driver and ODT using external reference resistor to ground\r\n⚫ Asynchronous RESET# pin for Power-up initialization sequence and reset function\r\n⚫ Programmable on-die termination ( | BGA | W638GU6QB-09 |
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W638GU6QB12I TR
Winbond
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1 | DRAM 8Gb DDR3L 1.35V SDRAM, x16, 800MHz, Industrial Temp, T&R | BGA | W638GU6QB12I TR |
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W638GU6QB-11
Winbond
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1 | ⚫ Backward compatible to VDD, VDDQ = 1.5V ± 0.075V\r\n⚫ Double Data Rate architecture: two data transfers per clock cycle\r\n⚫ Eight internal banks for concurrent operation\r\n⚫ 8 bit prefetch architecture\r\n⚫ CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n⚫ Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n⚫ Programmable read burst ordering: interleaved or nibble sequential\r\n⚫ Bi-directional, differential data strobes (DQS and DQS#) are transmitted / r | BGA | W638GU6QB-11 |
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W638GU6QB09I
Winbond
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1 | 4Gb DDR3 SDRAM 2133MHz VFBGA96 | BGA | W638GU6QB09I |
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W638GU6QB12I
Winbond
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1 | PACKAGE-96BGA | BGA | W638GU6QB12I |
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W638GU6QB-12
Winbond
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1 | 4Gb DDR3 SDRAM 1600MHz VFBGA96 | BGA | W638GU6QB-12 |
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W638GU6QB11I
Winbond
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1 | 4Gb DDR3 SDRAM 1866MHz VFBGA96 | BGA | W638GU6QB11I |
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