W9751 Footprint, Symbol and 3D Model search results

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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	W9751G6NB-18 Winbond	1	512Mb DDR2 SDRAM 1066MHz VFBGA84	BGA	W9751G6NB-18	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB25I Winbond	1	SDRAM - DDR2 Memory IC 512Mbit Parallel 400 MHz 57.5 ns 84-VFBGA (8x12.5)	BGA	W9751G6NB25I	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6KB25A Winbond	1	512Mb DDR2 SDRAM 800MHz WBGA84	BGA	W9751G6KB25A	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6KB-25 Winbond	1	IC SDRAM DDR2 512MBIT (32 x 16) 400MHZ 84BGA	BGA	W9751G6KB-25	3D model available Symbol and footprint available 3	1 Download Model

	W9751G6NB-25 Winbond	1	512Mb DDR2 SDRAM 800MHz VFBGA84	BGA	W9751G6NB-25	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB15I Winbond	1	512Mb DDR2 SDRAM 1333MHz VFBGA84	BGA	W9751G6NB15I	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB-18 Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB-18	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB25J Winbond	1	512Mb DDR2 SDRAM 800MHz VFBGA60	BGA	W9751G8NB25J	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB18J Winbond	1	512Mb DDR2 SDRAM 1066MHz VFBGA84	BGA	W9751G6NB18J	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB-25 Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB-25	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB18I Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB18I	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB18I Winbond	1	512Mb DDR2 SDRAM 1066MHz VFBGA84	BGA	W9751G6NB18I	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB-3J Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB-3J	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB25J Winbond	1	512Mb DDR2 SDRAM 800MHz VFBGA84	BGA	W9751G6NB25J	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB-3I Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB-3I	3D model available Symbol and footprint available 3	1 Download Model

	W9751G6NB-3I Winbond	1	DDR2 SDRAM 667MHz	BGA	W9751G6NB-3I	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB-3J Winbond	1	DDR2 SDRAM 667MHz	BGA	W9751G6NB-3J	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB-3 Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB-3	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB18J Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB18J	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB25I Winbond	1	 Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data	BGA	W9751G8NB25I	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB-3 Winbond	1	512Mb DDR2 SDRAM 667MHz VFBGA84	BGA	W9751G6NB-3	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6KB25K Winbond	1	512Mb DDR2 SDRAM 800MHz WBGA84	BGA	W9751G6KB25K	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB-15 Winbond	1	512Mb DDR2 SDRAM 1333MHz VFBGA84	BGA	W9751G6NB-15	3D model available Symbol and footprint available 3	1 Download Model
	W9751G6NB-25 TR Winbond	1	DRAM Chip DDR2 SDRAM 512Mbit	BGA	W9751G6NB-25 TR	3D model available Symbol and footprint available 3	1 Download Model
	W9751G8NB25A Winbond	1	512Mb DDR2 SDRAM 800MHz VFBGA60	BGA	W9751G8NB25A	3D model available Symbol and footprint available 3	1 Download Model
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