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EP1C20F400C8N - Intel

Description: FPGA Cyclone® Family 20060 Cells 275.03MHz 130nm Technology 1.5V 400-Pin FBGA

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EP1C20F400C8N - Intel PCB footprint - BGA - BGA - 400-Pin FineLine Ball-Grid Array (FBGA)
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3D Models
EP1C20F400C8N - Intel  - 3D model - BGA - 400-Pin FineLine Ball-Grid Array (FBGA)
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EP1C20F400C8N Details

  • Manufacturer Part Number:

    EP1C20F400C8N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    FBGA-400

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    275 MHz

  • JESD-30 Code:

    S-PBGA-B400

  • JESD-609 Code:

    e1

  • Length:

    21 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    2006

  • Number of Inputs:

    301

  • Number of Logic Cells:

    20060

  • Number of Outputs:

    301

  • Number of Terminals:

    400

  • Operating Temperature-Max:

    85 °C

  • Organization:

    2006 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA400,20X20,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.2 mm

  • Supply Voltage-Max:

    1.575 V

  • Supply Voltage-Min:

    1.425 V

  • Supply Voltage-Nom:

    1.5 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    21 mm

EP1C20F400C8N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the EP1C20F400C8N is -40°C to 100°C.
  • To implement a clock domain crossing (CDC) in the EP1C20F400C8N, you can use a synchronizer circuit or a FIFO-based CDC. The synchronizer circuit uses a pair of flip-flops to resynchronize the data, while the FIFO-based CDC uses a FIFO to buffer the data and a clock domain crossing circuit to synchronize the data.
  • The maximum frequency of operation for the EP1C20F400C8N is 250 MHz.
  • To optimize the power consumption of the EP1C20F400C8N, you can use power-aware design techniques such as clock gating, voltage scaling, and dynamic voltage and frequency scaling. You can also use the Intel Quartus II software to optimize the power consumption of the device.
  • The maximum current consumption of the EP1C20F400C8N is 1.5 A.

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EP1C20F400C8N Overview

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Part Image EP1C20F400C8N Altera Corporation

Field Programmable Gate Array, 2006 CLBS, 275MHz, 20060-Cell, PBGA400

Part Image EP1C20F400C8 Altera Corporation

Field Programmable Gate Array, 2006 CLBS, 275MHz, 20060-Cell, PBGA400

Part Image EP1C20F400I8 Altera Corporation

Field Programmable Gate Array, 2006 CLBS, 275MHz, 20060-Cell, PBGA400

Part Image EP1C20F400I8ES Altera Corporation

Field Programmable Gate Array, 20060 CLBs, 275MHz, PBGA400

Part Image EP1C20F400C8ES Intel Corporation

Field Programmable Gate Array, 20060 CLBs, 275MHz, PBGA400

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