Part Image

EP2S30F672C3N - Intel

Description: Stratix II Devices

Download EP2S30F672C3N Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
PCB Footprints
EP2S30F672C3N - Intel PCB footprint - BGA - BGA - 672-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Flat Top Single-Piece Lid - A:3.35
click to zoom
3D Models
EP2S30F672C3N - Intel  - 3D model - BGA - 672-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Flat Top Single-Piece Lid - A:3.35
click to zoom

EP2S30F672C3N Details

  • Manufacturer Part Number:

    EP2S30F672C3N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    35 X 35 MM, 1 MM PITCH, FBGA-672

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    717 MHz

  • Combinatorial Delay of a CLB-Max:

    4.45 ns

  • JESD-30 Code:

    S-PBGA-B672

  • JESD-609 Code:

    e1

  • Length:

    35 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    13552

  • Number of Inputs:

    500

  • Number of Logic Cells:

    33880

  • Number of Outputs:

    492

  • Number of Terminals:

    672

  • Operating Temperature-Max:

    85 °C

  • Organization:

    13552 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA672,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 90 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    BOTTOM

  • Width:

    35 mm

EP2S30F672C3N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the EP2S30F672C3N is -40°C to 100°C.
  • A reliable POR circuit can be implemented using a voltage supervisor IC, such as the MAX809, which can detect power-on and power-down sequences and generate a reset signal to the FPGA.
  • Intel recommends following the PCB layout guidelines outlined in the EP2S30F672C3N datasheet, including using a 4-layer PCB, placing decoupling capacitors near the FPGA, and minimizing signal trace lengths and vias.
  • To optimize timing closure, use the Intel Quartus II software to analyze and optimize the design's timing constraints, and consider using techniques such as pipelining, retiming, and clock domain crossing.
  • Intel recommends using the Intel Quartus II software and the USB-Blaster II download cable for JTAG configuration and debugging, as well as the SignalTap II logic analyzer for real-time signal analysis.

Trust Checks

This model has been verified by system checks.
System Verified
Sponsored

EP2S30F672C3N Overview

Use the download button to access the EP2S30F672C3N schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like EP2S3, or try a keyword search, such as Field Programmable Gate Arrays

Parts related to EP2S30F672C3N

Showing 0 results

EP2S30F672C3N Alternates

Showing results

Image Part Number Model
Part Image EP2S30F672C3 Altera Corporation

Field Programmable Gate Array, 13552 CLBs, 717MHz, 33880-Cell, CMOS, PBGA672

Part Image EP2S30F672C3N Altera Corporation

Field Programmable Gate Array, 13552 CLBs, 717MHz, 33880-Cell, CMOS, PBGA672