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EP2S60F1020C3 - Intel

Description: FPGA Stratix® II Family 60440 Cells 816.99MHz 90nm Technology 1.2V 1020-Pin FC-FBGA

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EP2S60F1020C3 - Intel - PCB symbol
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PCB Footprints
EP2S60F1020C3 - Intel PCB footprint - BGA - BGA - 1020-Pin FineLine Ball-Grid Array (FBGA), Option 1—Flip Chip
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EP2S60F1020C3 - Intel - 3D model - BGA - 1020-Pin FineLine Ball-Grid Array (FBGA), Option 1—Flip Chip
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EP2S60F1020C3 Details

  • Manufacturer Part Number:

    EP2S60F1020C3

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    33 X 33 MM, 1 MM PITCH, FBGA-1020

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    717 MHz

  • Combinatorial Delay of a CLB-Max:

    4.45 ns

  • JESD-30 Code:

    S-PBGA-B1020

  • JESD-609 Code:

    e0

  • Length:

    33 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    24176

  • Number of Inputs:

    718

  • Number of Logic Cells:

    60440

  • Number of Outputs:

    710

  • Number of Terminals:

    1020

  • Operating Temperature-Max:

    85 °C

  • Organization:

    24176 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA1020,32X32,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 90 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Lead (Sn/Pb)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    33 mm

EP2S60F1020C3 Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the EP2S60F1020C3 is -40°C to 100°C.
  • A reliable POR circuit can be implemented using a voltage supervisor IC, such as the MAX809, which can detect power-on and power-down sequences and generate a reset signal to the FPGA.
  • Intel recommends following the PCB layout guidelines outlined in the EP2S60F1020C3 datasheet, including using a 4-layer PCB, placing decoupling capacitors near the FPGA, and minimizing signal trace lengths.
  • To optimize timing closure, use the Intel Quartus II software to analyze and optimize the design, and consider using techniques such as pipelining, retiming, and register duplication.
  • The EP2S60F1020C3 has a maximum clock frequency of 300 MHz, and signal integrity can be affected by factors such as signal skew, jitter, and crosstalk. Careful PCB design and signal routing are essential to ensure signal integrity.

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EP2S60F1020C3 Overview

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EP2S60F1020C3 Alternates

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Part Image EP2S60F1020C3 Altera Corporation

Field Programmable Gate Array, 24176 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020
Part Image EP2S60F1020C3N Altera Corporation

Field Programmable Gate Array, 24176 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020
Part Image EP2S60F1020C3N Intel Corporation

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