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EP3C80F484C6N - Intel

Description: FPGA Cyclone® III Family 81264 Cells 500MHz 65nm Technology 1.2V 484-Pin FBGA

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EP3C80F484C6N - Intel PCB footprint - BGA - BGA - 484-Pin FineLine Ball-Grid Array (FBGA) - Wire Bond - A:2.40
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EP3C80F484C6N - Intel  - 3D model - BGA - 484-Pin FineLine Ball-Grid Array (FBGA) - Wire Bond - A:2.40
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EP3C80F484C6N Details

  • Manufacturer Part Number:

    EP3C80F484C6N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484

  • Country Of Origin:

    Mainland China, Malaysia, Taiwan, USA, Vietnam

  • ECCN Code:

    3A991

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    10

  • Clock Frequency-Max:

    472.5 MHz

  • JESD-30 Code:

    R-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    81264

  • Number of Inputs:

    295

  • Number of Logic Cells:

    81264

  • Number of Outputs:

    295

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    85 °C

  • Organization:

    81264 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    RECTANGULAR

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    23 mm

EP3C80F484C6N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the EP3C80F484C6N is -40°C to 100°C.
  • To implement a clock domain crossing (CDC) in the EP3C80F484C6N, use a synchronizer circuit or a FIFO-based CDC to ensure data integrity and prevent metastability issues.
  • The recommended power-on reset (POR) circuit for the EP3C80F484C6N is a simple RC circuit with a 1-2 ms delay to ensure proper device initialization.
  • To optimize the EP3C80F484C6N for low power consumption, use the Intel Quartus II software to enable power-saving features such as clock gating, voltage scaling, and dynamic voltage and frequency scaling (DVFS).
  • The maximum current draw for the EP3C80F484C6N is 1.5 A for the core voltage (VCC) and 0.5 A for the auxiliary voltage (VCCAUX).

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EP3C80F484C6N Overview

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Part Image EP3C80F484C6N Altera Corporation

Field Programmable Gate Array, 81264 CLBs, 472.5MHz, 81264-Cell, CMOS, PBGA484

Part Image EP3C80F484C6 Intel Corporation

Field Programmable Gate Array, 81264 CLBs, 472.5MHz, 81264-Cell, CMOS, PBGA484