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LM4050AEX3-3.3/V+T - Analog Devices

Description: Voltage References 50ppm/C Prec uPower Shunt V-Ref w/Rev

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LM4050AEX3-3.3/V+T - Analog Devices PCB footprint - SOT23 (3-Pin) - SOT23 (3-Pin) - X3+2
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LM4050AEX3-3.3/V+T - Analog Devices  - 3D model - SOT23 (3-Pin) - X3+2
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LM4050AEX3-3.3/V+T Details

  • Manufacturer Part Number:

    LM4050AEX3-3.3/V+T

  • Brand Name:

    Analog Devices Inc

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    3-SC70-N/A

  • Pin Count:

    3

  • Manufacturer Package Code:

    3-SC70-N/A

  • Country Of Origin:

    Japan, Mainland China, Malaysia, Philippines, Singapore, South Korea, Taiwan, Thailand, USA

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.60

  • Date Of Intro:

    2002-08-15

  • Manufacturer:

    Analog Devices Inc

  • YTEOL:

    8.5

  • Analog IC - Other Type:

    TWO TERMINAL VOLTAGE REFERENCE

  • JESD-30 Code:

    R-PDSO-G3

  • JESD-609 Code:

    e3

  • Length:

    2 mm

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Outputs:

    1

  • Number of Terminals:

    3

  • Operating Temperature-Max:

    125 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Voltage-Max:

    3.3033 V

  • Output Voltage-Min:

    3.2967 V

  • Output Voltage-Nom:

    3.3 V

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TSSOP

  • Package Equivalence Code:

    TSSOP3/6,.08

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.1 mm

  • Surface Mount:

    YES

  • Technology:

    BICMOS

  • Temp Coef of Voltage-Max:

    50 ppm/°C

  • Temperature Grade:

    AUTOMOTIVE

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Trim/Adjustable Output:

    NO

  • Voltage Tolerance-Max:

    0.1%

  • Width:

    1.25 mm

LM4050AEX3-3.3/V+T Frequently Asked Questions (FAQs)

  • A good PCB layout for the LM4050AEX3-3.3/V+T involves keeping the input and output capacitors close to the device, using a solid ground plane, and minimizing trace lengths and widths to reduce noise and inductance. A 4-layer PCB with a dedicated power plane and a solid ground plane is recommended.
  • To ensure stability, make sure to follow the recommended capacitor values and types, and keep the input and output capacitors close to the device. Also, ensure that the PCB layout is well-designed and does not introduce excessive inductance or noise. Additionally, the device should be operated within its recommended operating conditions.
  • The maximum input voltage that the LM4050AEX3-3.3/V+T can handle is 15V. Exceeding this voltage may damage the device.
  • The LM4050AEX3-3.3/V+T is rated for operation up to 125°C. However, the device's performance and reliability may degrade at high temperatures. It's recommended to derate the device's output current and voltage at high temperatures to ensure reliable operation.
  • The power dissipation of the LM4050AEX3-3.3/V+T can be calculated using the formula: Pd = (Vin - Vout) x Iout, where Vin is the input voltage, Vout is the output voltage, and Iout is the output current. Make sure to consider the device's thermal resistance and maximum junction temperature when calculating the power dissipation.

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LM4050AEX3-3.3/V+T Overview

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About Analog Devices

Analog Devices Inc. is a global leader in the design and manufacturing of analog, mixed-signal, and digital signal processing integrated circuits and software solutions for the industrial, automotive, healthcare, communications industries. Analog Devices serves a diverse range of markets including industrial, automotive, healthcare, energy, aerospace, defense, and consumer electronics industries. Analog Devices’ product portfolio includes a wide range of ICs, modules, and subsystems.

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