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XC3S1200E-4FG400I - AMD

Description: Spartan®-3E Field Programmable Gate Array (FPGA) IC 304 516096 19512 400-BGA

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XC3S1200E-4FG400I - AMD PCB footprint - BGA - BGA - 400-Ball Fine-Pitch BGA (FG400/FGG400)
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XC3S1200E-4FG400I - AMD  - 3D model - BGA - 400-Ball Fine-Pitch BGA (FG400/FGG400)
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XC3S1200E-4FG400I Details

  • Manufacturer Part Number:

    XC3S1200E-4FG400I

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    FBGA-400

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    111 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    0

  • Clock Frequency-Max:

    572 MHz

  • Combinatorial Delay of a CLB-Max:

    0.76 ns

  • JESD-30 Code:

    S-PBGA-B400

  • JESD-609 Code:

    e0

  • Length:

    21 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    2168

  • Number of Equivalent Gates:

    1200000

  • Number of Inputs:

    304

  • Number of Logic Cells:

    19512

  • Number of Outputs:

    132

  • Number of Terminals:

    400

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    2168 CLBS, 1200000 GATES

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA400,20X20,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    225

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.43 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 90 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Lead (Sn63Pb37)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    21 mm

XC3S1200E-4FG400I Frequently Asked Questions (FAQs)

  • The maximum operating frequency of XC3S1200E-4FG400I is 350 MHz.
  • You can implement DDR memory interface with XC3S1200E-4FG400I using the Xilinx MIG (Memory Interface Generator) tool, which provides a pre-designed and verified DDR memory interface IP core.
  • Yes, XC3S1200E-4FG400I is suitable for high-reliability applications, as it is fabricated using a 90nm process and has features such as error correction, CRC, and SEU mitigation.
  • XC3S1200E-4FG400I can be programmed using the Xilinx ISE Design Suite, which includes tools such as PlanAhead, ISE Project Navigator, and iMPACT.
  • The power consumption of XC3S1200E-4FG400I depends on the specific application and operating conditions. However, the typical power consumption is around 1.2W for a typical design.

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XC3S1200E-4FG400I Overview

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Part Image XC3S1200E-4FG400I AMD Xilinx

Field Programmable Gate Array, 2168 CLBs, 1200000 Gates, 572MHz, 19512-Cell, CMOS, PBGA400

Part Image XC3S1200E-4FGG400I AMD Xilinx

Field Programmable Gate Array, 2168 CLBs, 1200000 Gates, 572MHz, 19512-Cell, CMOS, PBGA400