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XC7A200T-2SBG484I - AMD

Description: XILINX - XC7A200T-2SBG484I - FPGA, ARTIX-7, 285 I/O, FCBGA-484

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XC7A200T-2SBG484I - AMD PCB footprint - BGA - BGA - SBG484
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XC7A200T-2SBG484I - AMD  - 3D model - BGA - SBG484
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XC7A200T-2SBG484I Details

  • Manufacturer Part Number:

    XC7A200T-2SBG484I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    BGA-484

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    19 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    14

  • Clock Frequency-Max:

    1286 MHz

  • Combinatorial Delay of a CLB-Max:

    1.05 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    19 mm

  • Moisture Sensitivity Level:

    4

  • Number of CLBs:

    16825

  • Number of Inputs:

    285

  • Number of Logic Cells:

    215360

  • Number of Outputs:

    285

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    16825 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    FBGA

  • Package Equivalence Code:

    BGA484,22X22,32

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, FINE PITCH

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.44 mm

  • Supply Voltage-Max:

    1.05 V

  • Supply Voltage-Min:

    0.95 V

  • Supply Voltage-Nom:

    1 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 28 nm

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    19 mm

XC7A200T-2SBG484I Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the XC7A200T-2SBG484I is dependent on the specific design and implementation, but Xilinx recommends a maximum clock frequency of 350 MHz.
  • The XC7A200T-2SBG484I has a built-in DDR3 memory controller, and Xilinx provides a DDR3 memory interface IP core that can be used to implement a DDR3 memory interface. The IP core is available in the Vivado Design Suite.
  • The power consumption of the XC7A200T-2SBG484I depends on the specific design and implementation, but Xilinx provides a power estimator tool in the Vivado Design Suite that can be used to estimate the power consumption of the FPGA.
  • The XC7A200T-2SBG484I has a built-in PCIe endpoint block, and Xilinx provides a PCIe IP core that can be used to implement a PCIe interface. The IP core is available in the Vivado Design Suite.
  • The XC7A200T-2SBG484I has GTX transceivers that can operate at up to 12.5 Gbps, and the maximum bandwidth is dependent on the specific design and implementation.

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XC7A200T-2SBG484I Overview

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Part Image XC7A200T-2SBG484I AMD Xilinx

Field Programmable Gate Array, 16825 CLBs, 1286MHz, 215360-Cell, CMOS, PBGA484

Part Image XC7A200T-2SB484C AMD

Field Programmable Gate Array, PBGA484

Part Image XC7A200T-2SBG484C AMD Xilinx

Field Programmable Gate Array, 16825 CLBs, 1286MHz, 215360-Cell, CMOS, PBGA484

Part Image XC7A200T-2SB484C AMD Xilinx

Field Programmable Gate Array, PBGA484

Part Image XC7A200T-2SBV484C AMD Xilinx

Field Programmable Gate Array, 16825 CLBs, PBGA484

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